From: Jamin Lin <jamin_lin@aspeedtech.com>
To: "philmd@linaro.org" <philmd@linaro.org>,
"peterx@redhat.com" <peterx@redhat.com>,
"Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Kane Chen" <kane_chen@aspeedtech.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"Yanan Wang" <wangyanan55@huawei.com>,
"Zhao Liu" <zhao1.liu@intel.com>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: Jamin Lin <jamin_lin@aspeedtech.com>,
Troy Lee <troy_lee@aspeedtech.com>,
"flwu@google.com" <flwu@google.com>,
"nabihestefan@google.com" <nabihestefan@google.com>,
"farosas@suse.de" <farosas@suse.de>
Subject: [PATCH v4 14/17] hw/usb/hcd-ehci: Add ctrldssegment-default property
Date: Thu, 23 Apr 2026 05:18:22 +0000 [thread overview]
Message-ID: <20260423051804.362095-15-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20260423051804.362095-1-jamin_lin@aspeedtech.com>
When 64-bit addressing is supported, the Linux EHCI driver programs the
segment register to zero. See ehci_run function:
https://github.com/torvalds/linux/blob/master/drivers/usb/host/ehci-hcd.c
The driver comment also notes that descriptor structures allocated from
the DMA pool use segment zero semantics.
Descriptor memory is allocated using the DMA API. The platform driver
configures a 64-bit DMA mask so memory can be allocated above 4GB.
See ehci_platform_probe function:
https://github.com/torvalds/linux/blob/master/drivers/usb/host/ehci-platform.c
On AST2700 platforms, system DRAM is mapped above 4GB at 0x400000000.
As a result, descriptor addresses constructed directly from the guest
EHCI registers do not match the actual system address used by the
controller when fetching queue heads (QH) and queue element transfer
descriptors (qTD).
Add a ctrldssegment-default property so platforms can provide a
descriptor address offset when constructing descriptor addresses.
This allows systems where DRAM resides above 4GB to access EHCI
descriptors correctly.
The default value is zero, so existing machines are not affected.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/usb/hcd-ehci.h | 5 ++++-
hw/usb/hcd-ehci.c | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h
index 8e6a8cdfb0..3d57e1de5f 100644
--- a/hw/usb/hcd-ehci.h
+++ b/hw/usb/hcd-ehci.h
@@ -264,6 +264,7 @@ struct EHCIState {
uint32_t maxframes;
bool migrate_fetch_addr_64bit;
bool caps_64bit_addr;
+ uint32_t ctrldssegment_default;
/*
* EHCI spec version 1.0 Section 2.3
@@ -322,7 +323,9 @@ struct EHCIState {
DEFINE_PROP_BOOL("x-migrate-fetch-addr-64bit", _state, \
ehci.migrate_fetch_addr_64bit, true), \
DEFINE_PROP_BOOL("caps-64bit-addr", _state, \
- ehci.caps_64bit_addr, false)
+ ehci.caps_64bit_addr, false), \
+ DEFINE_PROP_UINT32("ctrldssegment-default", _state, \
+ ehci.ctrldssegment_default, 0)
extern const VMStateDescription vmstate_ehci;
diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c
index dfeb8ef70f..e8086f0432 100644
--- a/hw/usb/hcd-ehci.c
+++ b/hw/usb/hcd-ehci.c
@@ -1134,6 +1134,7 @@ static void ehci_opreg_write(void *ptr, hwaddr addr,
" 64-bit addressing capability is disabled\n");
return;
}
+ val |= s->ctrldssegment_default;
break;
case ASYNCLISTADDR:
--
2.43.0
next prev parent reply other threads:[~2026-04-23 5:20 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-23 5:18 [PATCH v4 00/17] hw/usb/ehci: Add 64-bit descriptor addressing support Jamin Lin
2026-04-23 5:18 ` [PATCH v4 01/17] tests/functional/arm/test_aspeed_ast2600_sdk: Add USB EHCI test for AST2600 SDK Jamin Lin
2026-04-23 5:18 ` [PATCH v4 02/17] hw/usb/hcd-ehci: Remove unused EHCIfstn structure and dead code Jamin Lin
2026-04-23 5:18 ` [PATCH v4 03/17] hw/usb/hcd-ehci.h: Fix coding style issues reported by checkpatch Jamin Lin
2026-04-23 5:18 ` [PATCH v4 04/17] hw/usb/hcd-ehci.c: " Jamin Lin
2026-04-23 5:18 ` [PATCH v4 05/17] hw/usb/hcd-ehci.c: Replace fprintf(stderr, ...) with qemu_log_mask(LOG_GUEST_ERROR) Jamin Lin
2026-04-23 9:09 ` Cédric Le Goater
2026-04-23 5:18 ` [PATCH v4 06/17] hw/usb/hcd-ehci: Replace DPRINTF debug logs with trace events Jamin Lin
2026-04-23 5:18 ` [PATCH v4 07/17] hw/usb/hcd-ehci: Introduce common properties macro for sysbus and pci Jamin Lin
2026-04-23 5:18 ` [PATCH v4 08/17] hw/usb/hcd-ehci: Change descriptor addresses to 64-bit with migration compatibility Jamin Lin
2026-04-23 11:45 ` Cédric Le Goater
2026-04-24 3:53 ` Jamin Lin
2026-04-23 16:07 ` Peter Xu
2026-04-24 6:03 ` Jamin Lin
2026-04-23 5:18 ` [PATCH v4 09/17] hw/usb/hcd-ehci: Add property to advertise 64-bit addressing capability Jamin Lin
2026-04-23 5:18 ` [PATCH v4 10/17] hw/usb/hcd-ehci: Implement 64-bit QH descriptor addressing Jamin Lin
2026-04-23 5:18 ` [PATCH v4 11/17] hw/usb/hcd-ehci: Implement 64-bit qTD " Jamin Lin
2026-04-23 5:18 ` [PATCH v4 12/17] hw/usb/hcd-ehci: Implement 64-bit iTD " Jamin Lin
2026-04-23 5:18 ` [PATCH v4 13/17] hw/usb/hcd-ehci: Implement 64-bit siTD " Jamin Lin
2026-04-23 5:18 ` Jamin Lin [this message]
2026-04-23 9:04 ` [PATCH v4 14/17] hw/usb/hcd-ehci: Add ctrldssegment-default property Cédric Le Goater
2026-04-23 5:18 ` [PATCH v4 15/17] hw/arm/aspeed_ast27x0: Set EHCI ctrldssegment-default Jamin Lin
2026-04-23 9:04 ` Cédric Le Goater
2026-04-23 5:18 ` [PATCH v4 16/17] hw/arm/aspeed_ast27x0: Enable 64-bit EHCI DMA addressing Jamin Lin
2026-04-23 5:18 ` [PATCH v4 17/17] tests/functional/aarch64/test_aspeed_ast2700: Add USB EHCI test for AST2700 A1/A2 Jamin Lin
2026-04-23 9:05 ` Cédric Le Goater
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