From: Ping-Ke Shih <pkshih@realtek.com>
To: <linux-wireless@vger.kernel.org>
Cc: <dian_syuan0116@realtek.com>
Subject: [PATCH rtw-next 1/3] wifi: rtw89: pci: no need to wait CLK ready for RTL8922DE
Date: Fri, 24 Apr 2026 15:25:50 +0800 [thread overview]
Message-ID: <20260424072552.59220-2-pkshih@realtek.com> (raw)
In-Reply-To: <20260424072552.59220-1-pkshih@realtek.com>
The bit is to wait for CLK ready when entering PCIE L1SS. However, a
certain host might not enable CLK for a situation, causing device state
stuck and trigger PCIE SER. Unset this bit as default like earlier chips.
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
---
drivers/net/wireless/realtek/rtw89/pci.h | 2 ++
drivers/net/wireless/realtek/rtw89/pci_be.c | 12 ++++++++++++
2 files changed, 14 insertions(+)
diff --git a/drivers/net/wireless/realtek/rtw89/pci.h b/drivers/net/wireless/realtek/rtw89/pci.h
index e7da37b9da7d..d0d1e2b99698 100644
--- a/drivers/net/wireless/realtek/rtw89/pci.h
+++ b/drivers/net/wireless/realtek/rtw89/pci.h
@@ -33,6 +33,8 @@
#define RAC_REG_REV2 0x1B
#define BAC_CMU_EN_DLY_MASK GENMASK(15, 12)
#define PCIE_DPHY_DLY_25US 0x1
+#define RAC_ANA14 0x14
+#define EIEOS_L1SS_WAIT_CLKRDY BIT(2)
#define RAC_ANA19 0x19
#define B_PCIE_BIT_RD_SEL BIT(2)
#define RAC_REG_FLD_0 0x1D
diff --git a/drivers/net/wireless/realtek/rtw89/pci_be.c b/drivers/net/wireless/realtek/rtw89/pci_be.c
index dfffec1ff3c7..473d491eb3f4 100644
--- a/drivers/net/wireless/realtek/rtw89/pci_be.c
+++ b/drivers/net/wireless/realtek/rtw89/pci_be.c
@@ -83,6 +83,17 @@ static void _patch_pcie_power_wake_be(struct rtw89_dev *rtwdev, bool power_up)
rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, BIT_WAKE_CTRL_V1);
}
+static void _patch_pre_init_be(struct rtw89_dev *rtwdev)
+{
+ struct rtw89_hal *hal = &rtwdev->hal;
+
+ if (!(rtwdev->chip->chip_id == RTL8922D && hal->cid == RTL8922D_CID7090))
+ return;
+
+ rtw89_write16_clr(rtwdev, R_RAC_DIRECT_OFFSET_BE_LANE0_G2 +
+ RAC_ANA14 * RAC_MULT, EIEOS_L1SS_WAIT_CLKRDY);
+}
+
static void rtw89_pci_set_io_rcy_be(struct rtw89_dev *rtwdev)
{
const struct rtw89_pci_info *info = rtwdev->pci_info;
@@ -475,6 +486,7 @@ static int rtw89_pci_ops_mac_pre_init_be(struct rtw89_dev *rtwdev)
rtw89_pci_set_io_rcy_be(rtwdev);
_patch_pcie_power_wake_be(rtwdev, true);
+ _patch_pre_init_be(rtwdev);
rtw89_pci_ctrl_wpdma_pcie_be(rtwdev, false);
rtw89_pci_ctrl_trxdma_pcie_be(rtwdev, MAC_AX_PCIE_DISABLE,
MAC_AX_PCIE_DISABLE, MAC_AX_PCIE_DISABLE);
--
2.25.1
next prev parent reply other threads:[~2026-04-24 7:26 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-24 7:25 [PATCH rtw-next 0/3] wifi: rtw89: update hardware settings to fix interoperability Ping-Ke Shih
2026-04-24 7:25 ` Ping-Ke Shih [this message]
2026-04-29 5:48 ` [PATCH rtw-next 1/3] wifi: rtw89: pci: no need to wait CLK ready for RTL8922DE Ping-Ke Shih
2026-04-24 7:25 ` [PATCH rtw-next 2/3] wifi: rtw89: disable HTC field in AP mode Ping-Ke Shih
2026-04-24 7:25 ` [PATCH rtw-next 3/3] wifi: rtw89: disable CSI STBC for VHT 160MHz Ping-Ke Shih
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