From: Stefan Hajnoczi <stefanha@redhat.com>
To: alistair23@gmail.com
Cc: palmer@dabbelt.com, liwei1518@gmail.com,
daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com,
chao.liu.zevorn@gmail.com, qemu-riscv@nongnu.org,
qemu-devel@nongnu.org, alistair23@gmail.com,
Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [PULL 00/51] riscv-to-apply queue
Date: Wed, 29 Apr 2026 12:23:15 -0400 [thread overview]
Message-ID: <20260429162315.GA121017@fedora> (raw)
In-Reply-To: <20260429044752.4176397-1-alistair.francis@wdc.com>
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Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/11.1 for any user-visible changes.
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prev parent reply other threads:[~2026-04-29 16:24 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-29 4:47 [PULL 00/51] riscv-to-apply queue alistair23
2026-04-29 4:47 ` [PULL 01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI alistair23
2026-04-29 4:47 ` [PULL 02/51] util: export CRC32[C] lookup tables alistair23
2026-04-29 4:47 ` [PULL 03/51] target/riscv: add draft RISC-V Zbr ext as xbr0p93 alistair23
2026-04-29 4:47 ` [PULL 04/51] disas: diassemble RISC-V xlrbr (crc32) instructions alistair23
2026-04-29 4:47 ` [PULL 05/51] target/riscv: Use explicit little-endian LD/ST API alistair23
2026-04-29 4:47 ` [PULL 06/51] target/riscv: Make LQ and SQ use 128-bit ld/st alistair23
2026-04-29 4:47 ` [PULL 07/51] target/riscv: Remove MTTCG check for x-rv128 CPU model alistair23
2026-04-29 4:47 ` [PULL 08/51] target/riscv: Explode MO_TExx -> MO_TE | MO_xx (again) alistair23
2026-04-29 4:47 ` [PULL 09/51] target/riscv: Conceal MO_ALIGN|MO_TE within load_acquire / store_release alistair23
2026-04-29 4:47 ` [PULL 10/51] target/riscv: Factor tiny ldn() helper in gdbstub alistair23
2026-04-29 4:47 ` [PULL 11/51] target/riscv: Simplify riscv_cpu_gdb_write_register() alistair23
2026-04-29 4:47 ` [PULL 12/51] target/riscv: Expose mo_endian_env() alistair23
2026-04-29 4:47 ` [PULL 13/51] target/riscv: Have gdbstub consider CPU endianness alistair23
2026-04-29 4:47 ` [PULL 14/51] target/riscv: Replace MO_TE by mo_endian (MIPS extension) alistair23
2026-04-29 4:47 ` [PULL 15/51] target/riscv: Replace MO_TE by mo_endian (Zilsd extension) alistair23
2026-04-29 4:47 ` [PULL 16/51] target/riscv: Replace MO_TE by mo_endian (Zalasr extension) alistair23
2026-04-29 4:47 ` [PULL 17/51] target/riscv: Replace MO_TE -> MO_LE alistair23
2026-04-29 4:47 ` [PULL 18/51] target/riscv: Use MO_LE for instruction fetch alistair23
2026-04-29 4:47 ` [PULL 19/51] configs/targets: Forbid RISC-V to use legacy native endianness APIs alistair23
2026-04-29 4:47 ` [PULL 20/51] hw/riscv/riscv-iommu-hpm: Fix irq_overflow_left residual value bug alistair23
2026-04-29 4:47 ` [PULL 21/51] hw/riscv/riscv-iommu: Add IPSR.PMIP RW1C support alistair23
2026-04-29 4:47 ` [PULL 22/51] hw/riscv/virt-acpi-build.c: Use kvm timer frequency when kvm enabled alistair23
2026-04-29 4:47 ` [PULL 23/51] target/riscv: fix stale ptshift and base on page walk restart alistair23
2026-04-29 4:47 ` [PULL 24/51] hw/intc: fix heap OOB in ACLINT MTIMER multi-socket alistair23
2026-04-29 4:47 ` [PULL 25/51] riscv_htif: reject invalid signature ranges (end <= begin) alistair23
2026-04-30 18:14 ` Michael Tokarev
2026-04-29 4:47 ` [PULL 26/51] target/riscv: preserve RV32 henvcfgh on henvcfg writes alistair23
2026-04-29 4:47 ` [PULL 27/51] target/riscv: Add cfg properties for Zvfbfa extensions alistair23
2026-04-29 4:47 ` [PULL 28/51] target/riscv: Add the Zvfbfa extension implied rule alistair23
2026-04-29 4:47 ` [PULL 29/51] target/riscv: rvv: Add new VTYPE CSR field - altfmt alistair23
2026-04-29 4:47 ` [PULL 30/51] target/riscv: rvv: Introduce reset_ill_vtype to reset illegal vtype CSR alistair23
2026-04-29 4:47 ` [PULL 31/51] target/riscv: Use the tb->cs_base as the extend tb flags alistair23
2026-04-29 4:47 ` [PULL 32/51] target/riscv: Introduce altfmt into DisasContext alistair23
2026-04-29 4:47 ` [PULL 33/51] target/riscv: Introduce BF16 canonical NaN for Zvfbfa extension alistair23
2026-04-29 4:47 ` [PULL 34/51] target/riscv: rvv: Support Zvfbfa vector bf16 operations alistair23
2026-04-29 4:47 ` [PULL 35/51] target/riscv: Expose Zvfbfa extension as a cpu property alistair23
2026-04-29 4:47 ` [PULL 36/51] target/riscv: rvv: Allow fractional LMUL on vector SHA instructions alistair23
2026-04-29 4:47 ` [PULL 37/51] target/riscv: tt-ascalon: Add Tenstorrent mvendorid alistair23
2026-04-29 4:47 ` [PULL 38/51] hw/riscv/boot: Warn if a ELF format file is loaded as a binary alistair23
2026-04-29 4:47 ` [PULL 39/51] target/riscv: fix RV32 stateen CSR handling alistair23
2026-04-29 4:47 ` [PULL 40/51] target/riscv: Initialize riscv_excp_names[] and riscv_intr_names[] using designated initializer alistair23
2026-04-29 4:47 ` [PULL 41/51] target/riscv: Mask xepc[0] only when Zc* extension is enabled alistair23
2026-04-29 4:47 ` [PULL 42/51] target/riscv: Generate access fault if sc comparison fails alistair23
2026-04-29 4:47 ` [PULL 43/51] target/riscv: Don't OR mip.SEIP when mvien is one alistair23
2026-04-29 4:47 ` [PULL 44/51] target/riscv: Use ELEN for Fractional LMUL check alistair23
2026-04-29 4:47 ` [PULL 45/51] target/riscv: fix address masking alistair23
2026-04-29 4:47 ` [PULL 46/51] target/riscv: Add a helper to return the current effective priv mode alistair23
2026-04-29 4:47 ` [PULL 47/51] target/riscv: Fix pointer masking PMM field selection logic alistair23
2026-04-29 4:47 ` [PULL 48/51] target/riscv: Fix pointer masking for virtual-machine load/store insns alistair23
2026-04-29 4:47 ` [PULL 49/51] target/riscv: Rename riscv_pm_get_virt_pmm() to riscv_pm_get_vm_ldst_pmm() alistair23
2026-04-29 4:47 ` [PULL 50/51] target/riscv: Fix pointer masking translation mode check bug alistair23
2026-04-29 4:47 ` [PULL 51/51] target/riscv: rvv: Handle mask/source overlap of vector reduction instructions alistair23
2026-04-29 16:23 ` Stefan Hajnoczi [this message]
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