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Wed, 29 Apr 2026 18:33:31 +0000 (GMT) Received: from localhost.localdomain (unknown [9.39.31.77]) by smtpav06.fra02v.mail.ibm.com (Postfix) with ESMTP; Wed, 29 Apr 2026 18:33:31 +0000 (GMT) From: Harsh Prateek Bora To: qemu-devel@nongnu.org Cc: Aditya Gupta , Hari Bathini , Sourabh Jain , Shivang Upadhyay Subject: [PULL 02/13] ppc/mpipl: Implement S0 SBE interrupt Date: Thu, 30 Apr 2026 00:02:52 +0530 Message-ID: <20260429183310.12455-3-harshpb@linux.ibm.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260429183310.12455-1-harshpb@linux.ibm.com> References: <20260429183310.12455-1-harshpb@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Authority-Analysis: v=2.4 cv=CIIamxrD c=1 sm=1 tr=0 ts=69f24f02 cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=A5OVakUREuEA:10 a=f7IdgyKtn90A:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=RzCfie-kr_QcCd8fBx8p:22 a=VwQbUJbxAAAA:8 a=VnNF1IyMAAAA:8 a=0EWF82VJ2pR67mXLOX4A:9 X-Proofpoint-ORIG-GUID: oTeEaW6mz1fpJOrT2dd8bcEVgu7GqJDo X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI5MDE4NCBTYWx0ZWRfX9wPxH8Db3943 0d0Glqs0rs6wcIW+7uUrwfX10ZvuimZwEyDS6pJkz5QSKygX0UEfaJNzGesmSnl6cHRNuIg3t8/ Xr9EUoSydDrhIQMQks25XXcdRgcD+Hmm8f8iC2CVz1z6R1PABlzixoB0VO0SDBTBmTTef848Ez4 HARdk0W4OVu6bPnu4DJzyZSATU9J1/12MSOE8MU0a7bl8CQ+LbioeYqVIH3frmhUXle7qvgxBek ZoXk055OanVFb6Hn7rfxqw6WL1BuxIzmjr/fkzrOa2BH1yDPskgtgIbp7esf6N27qVFJ27O4C0T rjugRzjjdolHvi8AtnquzdQA+S0xqyTo8M59SqJM76M1Srqqm1h89Cv+cEJjMKDlGh3PudbWl7+ WMeTFAgISGkl24ab/rUMIYZqB8jeZJP6YNFmins0YYO4wb1kOjuFOnXK4KTmy5o3fQQO06BDk9S LMP04K4KyY5c0f8Ua7A== X-Proofpoint-GUID: oTeEaW6mz1fpJOrT2dd8bcEVgu7GqJDo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-29_01,2026-04-28_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 malwarescore=0 suspectscore=0 adultscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604290184 Received-SPF: pass client-ip=148.163.158.5; envelope-from=harshpb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Aditya Gupta During MPIPL (aka fadump), after a kernel crash, the kernel does opal_cec_reboot2 opal call, signifying an abnormal termination. When OPAL receives this opal call, it further triggers SBE S0 interrupt, to trigger a MPIPL boot. Currently S0 interrupt is unimplemented in QEMU. Implement S0 interrupt as 'pause_vcpus' + 'guest_reset' in QEMU, as the SBE's implementation of S0 seems to be basically "stop all clocks" and then "host reset". pause_vcpus is done in a later patch when register preserving support is added See 'stopClocksS0' in SBE source code for more information. Also log both S0 and S1 interrupts. Reviewed-by: Hari Bathini Reviewed-by: Sourabh Jain Signed-off-by: Aditya Gupta Tested-by: Shivang Upadhyay Link: https://lore.kernel.org/qemu-devel/20260424083837.214947-3-adityag@linux.ibm.com Signed-off-by: Harsh Prateek Bora --- include/hw/ppc/pnv.h | 5 +++++ include/hw/ppc/pnv_mpipl.h | 19 +++++++++++++++++++ hw/ppc/pnv_mpipl.c | 26 ++++++++++++++++++++++++++ hw/ppc/pnv_sbe.c | 29 +++++++++++++++++++++++++++++ hw/ppc/meson.build | 1 + 5 files changed, 80 insertions(+) create mode 100644 include/hw/ppc/pnv_mpipl.h create mode 100644 hw/ppc/pnv_mpipl.c diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index ce3ce73b53..19c7170e74 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -25,6 +25,7 @@ #include "hw/core/sysbus.h" #include "hw/ipmi/ipmi.h" #include "hw/ppc/pnv_pnor.h" +#include "hw/ppc/pnv_mpipl.h" #define TYPE_PNV_CHIP "pnv-chip" @@ -113,6 +114,7 @@ struct PnvMachineState { bool lpar_per_core; Notifier machine_init_done; + MpiplPreservedState mpipl_state; }; PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id); @@ -292,4 +294,7 @@ void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor); #define PNV11_OCC_SENSOR_BASE(chip) PNV10_OCC_SENSOR_BASE(chip) +/* MPIPL helpers */ +void do_mpipl_preserve(PnvMachineState *pnv); + #endif /* PPC_PNV_H */ diff --git a/include/hw/ppc/pnv_mpipl.h b/include/hw/ppc/pnv_mpipl.h new file mode 100644 index 0000000000..61ef7ef8fe --- /dev/null +++ b/include/hw/ppc/pnv_mpipl.h @@ -0,0 +1,19 @@ +/* + * Emulation of MPIPL (Memory Preserving Initial Program Load), aka fadump + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef PNV_MPIPL_H +#define PNV_MPIPL_H + +#include + +typedef struct MpiplPreservedState MpiplPreservedState; + +/* Preserved state to be saved in PnvMachineState */ +struct MpiplPreservedState { + bool is_next_boot_mpipl; +}; + +#endif diff --git a/hw/ppc/pnv_mpipl.c b/hw/ppc/pnv_mpipl.c new file mode 100644 index 0000000000..d8c9b7a428 --- /dev/null +++ b/hw/ppc/pnv_mpipl.c @@ -0,0 +1,26 @@ +/* + * Emulation of MPIPL (Memory Preserving Initial Program Load), aka fadump + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "system/runstate.h" +#include "hw/ppc/pnv.h" +#include "hw/ppc/pnv_mpipl.h" + +void do_mpipl_preserve(PnvMachineState *pnv) +{ + /* Mark next boot as Memory-preserving boot */ + pnv->mpipl_state.is_next_boot_mpipl = true; + + /* + * Do a guest reset. + * Next reset will see 'is_next_boot_mpipl' as true, and trigger MPIPL + * + * Requirement: + * GUEST_RESET is expected to NOT clear the memory, as is the case when + * this is merged + */ + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); +} diff --git a/hw/ppc/pnv_sbe.c b/hw/ppc/pnv_sbe.c index 247617338a..5a2b3342d1 100644 --- a/hw/ppc/pnv_sbe.c +++ b/hw/ppc/pnv_sbe.c @@ -26,6 +26,9 @@ #include "hw/ppc/pnv.h" #include "hw/ppc/pnv_xscom.h" #include "hw/ppc/pnv_sbe.h" +#include "hw/ppc/pnv_mpipl.h" +#include "system/cpus.h" +#include "system/runstate.h" #include "trace.h" /* @@ -113,11 +116,37 @@ static uint64_t pnv_sbe_power9_xscom_ctrl_read(void *opaque, hwaddr addr, static void pnv_sbe_power9_xscom_ctrl_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { + PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); + PnvSBE *sbe = opaque; uint32_t offset = addr >> 3; trace_pnv_sbe_xscom_ctrl_write(addr, val); switch (offset) { + case SBE_CONTROL_REG_RW: + switch (val) { + case SBE_CONTROL_REG_S0: + qemu_log_mask(LOG_UNIMP, "SBE: S0 Interrupt triggered\n"); + + pnv_sbe_set_host_doorbell(sbe, sbe->host_doorbell | SBE_HOST_RESPONSE_MASK); + + /* Preserve memory regions and CPU state, if MPIPL is registered */ + do_mpipl_preserve(pnv); + + /* + * Control may not come back here as 'do_mpipl_preserve' triggers + * a guest reboot + */ + break; + case SBE_CONTROL_REG_S1: + qemu_log_mask(LOG_UNIMP, "SBE: S1 Interrupt triggered\n"); + break; + default: + qemu_log_mask(LOG_UNIMP, + "SBE: CONTROL_REG_RW: Unknown value: Ox%." + HWADDR_PRIx "\n", val); + } + break; default: qemu_log_mask(LOG_UNIMP, "SBE Unimplemented register: Ox%" HWADDR_PRIx "\n", addr >> 3); diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build index f7dac87a2a..c61fba4ec8 100644 --- a/hw/ppc/meson.build +++ b/hw/ppc/meson.build @@ -56,6 +56,7 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files( 'pnv_pnor.c', 'pnv_nest_pervasive.c', 'pnv_n1_chiplet.c', + 'pnv_mpipl.c', )) # PowerPC 4xx boards ppc_ss.add(when: 'CONFIG_PPC405', if_true: files( -- 2.52.0