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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48a8fede418sm12863335e9.6.2026.05.01.03.15.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 May 2026 03:15:32 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/28] hvf: arm: allow exposing minimal PMU for kernel-irqchip=on Date: Fri, 1 May 2026 11:14:58 +0100 Message-ID: <20260501101505.3485916-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260501101505.3485916-1-peter.maydell@linaro.org> References: <20260501101505.3485916-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mohamed Mediouni When running with the Apple vGIC, a minimum PMU is exposed by Hypervisor.framework if a valid PMUVer register value is set. That PMU isn't exposed otherwise. Signed-off-by: Mohamed Mediouni Reviewed-by: Philippe Mathieu-Daudé Message-id: 20260429190532.26538-9-mohamed@unpredictable.fr Signed-off-by: Peter Maydell --- target/arm/hvf/hvf.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 9d64f2e1a5..390a3529ff 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1145,6 +1145,25 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) clamp_id_aa64mmfr0_parange_to_ipa_size(&host_isar); + /* + * Windows wants at least the PMU's cycles counter to be available. + * + * With kernel-irqchip=off, we "emulate" the cycles counter + * in reference to time in QEMU. Having that, even with + * ID_AA64DFR0_EL1.PMUVer = 0 is enough to make Windows happy. + * + * As it's a very inaccurate implementation with its only purpose + * being making Windows boot, expose ID_AA64DFR0_EL1.PMUVer = 0 + * when kernel-irqchip=off. + * + * When kernel-irqchip=on *and* ID_AA64DFR0_EL1.PMUVer = 1, + * the OS provides its own PMU emulation, which is currently + * a cycles counter only emulation. + */ + if (hvf_irqchip_in_kernel()) { + FIELD_DP64_IDREG(&host_isar, ID_AA64DFR0, PMUVER, 0x1); + } + ahcf->isar = host_isar; /* -- 2.43.0