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[47.54.130.67]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8b53c7accddsm23110796d6.36.2026.05.01.06.00.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 May 2026 06:00:07 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1wInTS-00000005DWr-2vHb; Fri, 01 May 2026 10:00:06 -0300 Date: Fri, 1 May 2026 10:00:06 -0300 From: Jason Gunthorpe To: Mostafa Saleh Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, iommu@lists.linux.dev, catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, joro@8bytes.org, jean-philippe@linaro.org, mark.rutland@arm.com, qperret@google.com, tabba@google.com, vdonnefort@google.com, sebastianene@google.com, keirf@google.com Subject: Re: [PATCH v6 08/25] KVM: arm64: iommu: Shadow host stage-2 page table Message-ID: <20260501130006.GF6912@ziepe.ca> References: <20260501111928.259252-1-smostafa@google.com> <20260501111928.259252-9-smostafa@google.com> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260501111928.259252-9-smostafa@google.com> On Fri, May 01, 2026 at 11:19:10AM +0000, Mostafa Saleh wrote: > Create a page-table for the IOMMU that shadows the host CPU stage-2 > to establish DMA isolation. Is there a reason you can't just use the CPU S2 for the iommu? ie the CCA RMM is doing that, it is how ARM imagined this stuff would work. Once you start supporting DMA like this you have no choice but to keep a fully populated at all times S2 around, why not use that for the CPU too to avoid faults? I guess there is a reason, but maybe explain in the commit message? It sure would be simpler, you wouldn't have to mess with iopgtable at all... Jason