From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF1FC2192F9 for ; Sun, 3 May 2026 07:36:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777793784; cv=none; b=tVdOJmo5b8QibjEGEq93PyUsiR+DMzXINPHl/dolHKxDEgij5u+k8l34GGIO8AZmz4QWcIwI+d0N7Uq0gekg4QyPXAKhBdliAutqvazOHGpUt6B/kaufCTnjqzDBL8x4IJtcSjqohuCPicGwyQb/bDE2rxOFQGW3CBwW1AnrSpQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777793784; c=relaxed/simple; bh=DZOTdwJV9MvKi33AOPezheGWGQZHZrn7rmZ5HznDBRM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:content-type; b=jsU73C/hhrBQ1wg1i21TUpHdMG+scZtCppN1UIbs2nthnUZyIjKorjmGOy0gJtib8k/zkUFLmPGhyNG1WJmJEFz27APJIMQtXLSGBbPrn2uTsKC16xY0+wu3aFFpK77Vvlpo/y8Ohi125FAkNiaTomPhbCXsRW3f4q/tXUE44bY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=VSuBHbxh; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="VSuBHbxh" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1777793781; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qb3QW9P09q68kQSB3KrvBidDZUkt/y6oNpcfFLBp4WY=; b=VSuBHbxhzIDV2IC/zF1+krFTBTCzcmzgTlYWcH4rwSIEgvSOYZr6EuTEaJ7dNacPSAGhFf MvvQLU3uERc28aproGbpFHL6rTHMJDtXjogSUqhCTjbHqN8pP35VuqyrgD9geiTzSMba5g STLLnv7fR9ZYEuW5tqPgnwN6yvxfa4o= Received: from mx-prod-mc-03.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-80-1tdrefN_OA6tJm76iHJILA-1; Sun, 03 May 2026 03:36:17 -0400 X-MC-Unique: 1tdrefN_OA6tJm76iHJILA-1 X-Mimecast-MFC-AGG-ID: 1tdrefN_OA6tJm76iHJILA_1777793776 Received: from mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.93]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id EFC4919560AA; Sun, 3 May 2026 07:36:15 +0000 (UTC) Received: from laptop.redhat.com (unknown [10.44.48.25]) by mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 0F9C81800577; Sun, 3 May 2026 07:36:10 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, cohuck@redhat.com, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v4 04/17] arm/cpu: Add infra to handle generated ID register definitions Date: Sun, 3 May 2026 09:33:24 +0200 Message-ID: <20260503073541.790215-5-eric.auger@redhat.com> In-Reply-To: <20260503073541.790215-1-eric.auger@redhat.com> References: <20260503073541.790215-1-eric.auger@redhat.com> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 X-Mimecast-MFC-PROC-ID: ZPdlKreJBEj1QIPntpRY7ycJ8xjkjTBrnXvduyXQhLI_1777793776 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: 8bit content-type: text/plain; charset="US-ASCII"; x-default=true The known ID regs are populated in a new initialization function named initialize_cpu_sysreg_properties(). That code will be automatically generated from AARCHMRS Registers.json. For the time being let's just describe a single id reg, CTR_EL0. In this description we only care about non RES/RAZ fields, ie. named fields. The registers are populated in an array indexed by ARMIDRegisterIdx and their fields are added in a sorted list. [CH: adapted to reworked register storage] Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- target/arm/cpu-idregs.h | 59 ++++++++++++++++++++++++++++++ target/arm/cpu-sysreg-properties.c | 30 +++++++++++++++ target/arm/cpu64.c | 3 ++ target/arm/meson.build | 3 +- 4 files changed, 94 insertions(+), 1 deletion(-) create mode 100644 target/arm/cpu-idregs.h create mode 100644 target/arm/cpu-sysreg-properties.c diff --git a/target/arm/cpu-idregs.h b/target/arm/cpu-idregs.h new file mode 100644 index 0000000000..4a9034594d --- /dev/null +++ b/target/arm/cpu-idregs.h @@ -0,0 +1,59 @@ +/* + * handle ID registers and their fields + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef ARM_CPU_CUSTOM_H +#define ARM_CPU_CUSTOM_H + +#include "qemu/osdep.h" +#include "qemu/error-report.h" +#include "cpu.h" +#include "cpu-sysregs.h" + +typedef struct ARM64SysRegField { + const char *name; /* name of the field, for instance CTR_EL0_IDC */ + ARMIDRegisterIdx index; /* parent register, e.g. CTR_EL0_IDX */ + int lower; /* lowest bit number of the field in the register */ + int upper; /* highest bit number */ +} ARM64SysRegField; + +typedef struct ARM64SysReg { + const char *name; /* name of the sysreg, for instance CTR_EL0 */ + ARMSysRegs sysreg; + ARMIDRegisterIdx index; /* register index, e.g. CTR_EL0_IDX */ + GList *fields; /* list of named fields, excluding RES* */ +} ARM64SysReg; + +void initialize_cpu_sysreg_properties(void); + +/* + * List of exposed ID regs (automatically populated from AARCHMRS Registers.json) + */ +extern ARM64SysReg arm64_id_regs[NUM_ID_IDX]; + +/* Allocate a new field and insert it at the head of the @reg list */ +static inline GList *arm64_sysreg_add_field(ARM64SysReg *reg, const char *name, + uint8_t min, uint8_t max) { + + ARM64SysRegField *field = g_new0(ARM64SysRegField, 1); + + field->name = name; + field->lower = min; + field->upper = max; + field->index = reg->index; + + reg->fields = g_list_append(reg->fields, field); + return reg->fields; +} + +static inline ARM64SysReg *arm64_sysreg_get(ARMIDRegisterIdx index) +{ + ARM64SysReg *reg = &arm64_id_regs[index]; + + reg->index = index; + reg->sysreg = id_register_sysreg[index]; + return reg; +} + +#endif diff --git a/target/arm/cpu-sysreg-properties.c b/target/arm/cpu-sysreg-properties.c new file mode 100644 index 0000000000..5cc06c8f24 --- /dev/null +++ b/target/arm/cpu-sysreg-properties.c @@ -0,0 +1,30 @@ +/* + * QEMU ARM CPU SYSREG PROPERTIES + * will be automatically generated + * + * Copyright (c) Red Hat, Inc. 2026 + * + */ + + /* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include "cpu-idregs.h" + +ARM64SysReg arm64_id_regs[NUM_ID_IDX]; + +void initialize_cpu_sysreg_properties(void) +{ + memset(arm64_id_regs, 0, sizeof(ARM64SysReg) * NUM_ID_IDX); + /* CTR_EL0 */ + ARM64SysReg *CTR_EL0 = arm64_sysreg_get(CTR_EL0_IDX); + CTR_EL0->name = "CTR_EL0"; + arm64_sysreg_add_field(CTR_EL0, "TminLine", 32, 37); + arm64_sysreg_add_field(CTR_EL0, "DIC", 29, 29); + arm64_sysreg_add_field(CTR_EL0, "IDC", 28, 28); + arm64_sysreg_add_field(CTR_EL0, "CWG", 24, 27); + arm64_sysreg_add_field(CTR_EL0, "ERG", 20, 23); + arm64_sysreg_add_field(CTR_EL0, "DminLine", 16, 19); + arm64_sysreg_add_field(CTR_EL0, "L1Ip", 14, 15); + arm64_sysreg_add_field(CTR_EL0, "IminLine", 0, 3); +} + diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index a93ad2da5a..b940842d9e 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -37,6 +37,7 @@ #include "hw/core/qdev-properties.h" #include "internals.h" #include "cpu-features.h" +#include "cpu-idregs.h" /* convert between _IDX and SYS_ */ #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \ @@ -906,6 +907,8 @@ static void aarch64_cpu_register_types(void) { size_t i; + initialize_cpu_sysreg_properties(); + for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { arm_cpu_register(&aarch64_cpus[i]); } diff --git a/target/arm/meson.build b/target/arm/meson.build index 192ac7c31e..e2f740e48f 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -9,7 +9,8 @@ arm_user_ss.add(files('gdbstub.c')) arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'cpu64.c', - 'gdbstub64.c' + 'gdbstub64.c', + 'cpu-sysreg-properties.c', )) arm_common_ss.add(files( -- 2.53.0