Re: [PATCH v7 04/20] perf: arm_pmuv3: Generalize counter bitmasks

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Missing synchronization for the tools mirrored header `tools/include/perf/arm_pmuv3.h`.
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commit 11c1a089e4abf2f887089a60dd977c70575ab494
Author: Colton Lewis <coltonlewis@google.com>

perf: arm_pmuv3: Generalize counter bitmasks

This commit renames the OVSR bitmasks to be more general since they apply
to enable and interrupt registers as well as overflow registers.

> diff --git a/include/linux/perf/arm_pmuv3.h b/include/linux/perf/arm_pmuv3.h
> index d698efba28a27..fd2a34b4a64d1 100644
> --- a/include/linux/perf/arm_pmuv3.h
> +++ b/include/linux/perf/arm_pmuv3.h
> @@ -224,14 +224,14 @@
>  				 ARMV8_PMU_PMCR_LC | ARMV8_PMU_PMCR_LP)
>  
>  /*
> - * PMOVSR: counters overflow flag status reg
> + * Counter bitmask layouts for overflow, enable, and interrupts
>   */
> -#define ARMV8_PMU_OVSR_P		GENMASK(30, 0)
> -#define ARMV8_PMU_OVSR_C		BIT(31)
> -#define ARMV8_PMU_OVSR_F		BIT_ULL(32) /* arm64 only */
> -/* Mask for writable bits is both P and C fields */
> -#define ARMV8_PMU_OVERFLOWED_MASK	(ARMV8_PMU_OVSR_P | ARMV8_PMU_OVSR_C | \
> -					ARMV8_PMU_OVSR_F)
> +#define ARMV8_PMU_CNT_MASK_P		GENMASK(30, 0)
> +#define ARMV8_PMU_CNT_MASK_C		BIT(31)
> +#define ARMV8_PMU_CNT_MASK_F		BIT_ULL(32) /* arm64 only */
> +#define ARMV8_PMU_CNT_MASK_ALL		(ARMV8_PMU_CNT_MASK_P | \
> +					 ARMV8_PMU_CNT_MASK_C | \
> +					 ARMV8_PMU_CNT_MASK_F)

This isn't a bug, but should tools/include/perf/arm_pmuv3.h also be updated
to reflect these macro renames?

The kernel maintains a mirrored copy of this header which is used by KVM
selftests (tools/testing/selftests/kvm/arm64/vpmu_counter_access.c). Keeping
the tools header synchronized helps avoid future build confusion for test
developers.

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Sashiko AI review · https://sashiko.dev/#/patchset/20260504211813.1804997-1-coltonlewis@google.com?part=4