From: sashiko-bot@kernel.org
To: "Hans Zhang" <18255117159@163.com>
Cc: wsa+renesas@sang-engineering.com, linux-pci@vger.kernel.org
Subject: Re: [PATCH v2 4/8] PCI: j721e: Set max_link_speed to enable 100 ms delay after link up
Date: Wed, 06 May 2026 21:12:22 +0000 [thread overview]
Message-ID: <20260506211223.0096BC2BCB0@smtp.kernel.org> (raw)
In-Reply-To: <20260506152346.166056-5-18255117159@163.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Compilation error due to incorrect member access operator on pointer `cdns_pcie`.
--
commit 0760ab7da4f40a125fce1efb70ebb7172483b069
Author: Hans Zhang <18255117159@163.com>
PCI: j721e: Set max_link_speed to enable 100 ms delay after link up
This commit sets the max_link_speed property to the maximum supported
link speed from the device tree to activate post-link delay logic. This
ensures a 100 ms delay after link training completes.
> diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> index bfdfe98d5aba7..ee85b8e04f5b8 100644
> --- a/drivers/pci/controller/cadence/pci-j721e.c
> +++ b/drivers/pci/controller/cadence/pci-j721e.c
> @@ -206,6 +206,7 @@ static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie,
> (pcie_get_link_speed(link_speed) == PCI_SPEED_UNKNOWN))
> link_speed = 2;
>
> + pcie->cdns_pcie.max_link_speed = link_speed;
Will this cause a compilation error? Looking at the definition of
struct j721e_pcie, cdns_pcie is declared as a pointer:
struct j721e_pcie {
struct cdns_pcie *cdns_pcie;
...
};
Since cdns_pcie is a pointer, does this code need to use the arrow
operator (pcie->cdns_pcie->max_link_speed) instead of the dot operator
to compile correctly?
> val = link_speed - 1;
> ret = regmap_update_bits(syscon, offset, GENERATION_SEL_MASK, val);
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260506152346.166056-1-18255117159@163.com?part=4
next prev parent reply other threads:[~2026-05-06 21:12 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-06 15:23 [PATCH v2 0/8] PCI: Add common helper for 100 ms delay after link training Hans Zhang
2026-05-06 15:23 ` [PATCH v2 1/8] PCI: Add pcie_wait_after_link_train() helper Hans Zhang
2026-05-06 15:34 ` Biju Das
2026-05-06 16:16 ` Hans Zhang
2026-05-06 15:55 ` Manivannan Sadhasivam
2026-05-06 16:13 ` Hans Zhang
2026-05-06 20:18 ` sashiko-bot
2026-05-06 15:23 ` [PATCH v2 2/8] PCI: cadence: LGA: Add max_link_speed field and 100 ms delay after link training Hans Zhang
2026-05-06 15:31 ` Biju Das
2026-05-06 16:21 ` Hans Zhang
2026-05-06 16:27 ` Biju Das
2026-05-06 16:31 ` Hans Zhang
2026-05-06 16:03 ` Manivannan Sadhasivam
2026-05-06 16:14 ` Hans Zhang
2026-05-06 20:39 ` sashiko-bot
2026-05-06 15:23 ` [PATCH v2 3/8] PCI: cadence: HPA: Add " Hans Zhang
2026-05-06 21:05 ` sashiko-bot
2026-05-06 15:23 ` [PATCH v2 4/8] PCI: j721e: Set max_link_speed to enable 100 ms delay after link up Hans Zhang
2026-05-06 16:04 ` Manivannan Sadhasivam
2026-05-06 16:11 ` Hans Zhang
2026-05-06 16:51 ` Manivannan Sadhasivam
2026-05-06 21:12 ` sashiko-bot [this message]
2026-05-06 15:23 ` [PATCH v2 5/8] PCI: dwc: Use common pcie_wait_after_link_train() helper Hans Zhang
2026-05-06 15:23 ` [PATCH v2 6/8] PCI: aardvark: Add 100 ms delay after link training Hans Zhang
2026-05-06 21:48 ` sashiko-bot
2026-05-12 21:25 ` Pali Rohár
2026-05-13 7:00 ` Hans Zhang
2026-05-13 7:20 ` Pali Rohár
2026-05-13 7:34 ` Hans Zhang
2026-05-13 18:54 ` Pali Rohár
2026-05-15 15:04 ` Hans Zhang
2026-05-06 15:23 ` [PATCH v2 7/8] PCI: mediatek-gen3: " Hans Zhang
2026-05-06 22:14 ` sashiko-bot
2026-05-06 15:23 ` [PATCH v2 8/8] PCI: rzg3s-host: " Hans Zhang
2026-05-06 16:52 ` Claudiu Beznea
2026-05-09 16:25 ` Hans Zhang
2026-05-06 22:28 ` sashiko-bot
2026-05-14 12:19 ` kernel test robot
2026-05-14 12:50 ` kernel test robot
2026-05-14 14:22 ` kernel test robot
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