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[124.158.97.178]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2babadf1242sm9087045ad.66.2026.05.06.21.39.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 May 2026 21:39:41 -0700 (PDT) From: Nicholas Piggin To: Alistair Francis , Daniel Henrique Barboza Cc: Nicholas Piggin , Chao Liu , Michael Ellerman , Joel Stanley , Anirudh Srinivasan , Portia Stephens , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v5 0/9] hw/riscv: Add the Tenstorrent Atlantis machine Date: Thu, 7 May 2026 14:38:28 +1000 Message-ID: <20260507043838.45652-1-npiggin@gmail.com> X-Mailer: git-send-email 2.53.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Introducing Tenstorrent Atlantis! The Tenstorrent Atlantis platform is a collaboration between Tenstorrent and CoreLab Technology. It is based on the Atlantis SoC, which includes the Ascalon-X CPU and other IP from Tenstorrent and CoreLab Technology. The Tenstorrent Ascalon-X is a high performance 64-bit RVA23 compliant RISC-V CPU. I will taking over this series while Joel is away. Many thanks to the reviewers on v4, here: https://lore.kernel.org/qemu-devel/20260425131721.932250-1-joel@jms.id.au/T/#mb1ef2824c2f1f37bf4574dc1ef0fb95566c3a2f2 Changes since v4: - Drop PCI, to rewok with Designware controller in a later patch. - Drop I2C, the model had significant changes so I will work on that independently and we can bring that back in Atlantis later. - Move the OpenSBI dummy payload hack into tt-atlantis specific code. - Remove AIA MAINTAINERS entry since it is already covered. - Update microchip_pfsoc to use new discontig boot_info API. - Update changelog to explain tt-atlantis machine DTB. Thanks, Nick Joel Stanley (3): hw/riscv/virt: Move AIA initialisation to helper file hw/riscv/aia: Provide number of irq sources hw/riscv: Add Tenstorrent Atlantis machine Nicholas Piggin (6): hw/riscv/boot: Describe discontiguous memory in boot_info hw/riscv/boot: Account for discontiguous memory when loading firmware target/riscv: tt-ascalon: Enable Zkr extension target/riscv: tt-ascalon: Enable Svadu by removing Svade hw/riscv/atlantis: Provide a simple halting payload tests/functional/riscv64: Add tt-atlantis tests MAINTAINERS | 11 + docs/system/riscv/tt_atlantis.rst | 32 + docs/system/target-riscv.rst | 1 + hw/riscv/Kconfig | 10 + hw/riscv/aia.c | 93 +++ hw/riscv/aia.h | 25 + hw/riscv/boot.c | 34 +- hw/riscv/meson.build | 3 +- hw/riscv/microchip_pfsoc.c | 8 +- hw/riscv/opentitan.c | 6 +- hw/riscv/shakti_c.c | 6 +- hw/riscv/sifive_u.c | 6 +- hw/riscv/spike.c | 6 +- hw/riscv/tt_atlantis.c | 583 +++++++++++++++++++ hw/riscv/virt-acpi-build.c | 27 +- hw/riscv/virt.c | 96 +-- hw/riscv/xiangshan_kmh.c | 6 +- include/hw/riscv/boot.h | 12 +- include/hw/riscv/tt_atlantis.h | 51 ++ include/hw/riscv/virt.h | 2 +- roms/seabios-hppa | 2 +- target/riscv/cpu.c | 2 +- tests/functional/riscv64/meson.build | 1 + tests/functional/riscv64/test_opensbi.py | 4 + tests/functional/riscv64/test_tt_atlantis.py | 57 ++ 25 files changed, 975 insertions(+), 109 deletions(-) create mode 100644 docs/system/riscv/tt_atlantis.rst create mode 100644 hw/riscv/aia.c create mode 100644 hw/riscv/aia.h create mode 100644 hw/riscv/tt_atlantis.c create mode 100644 include/hw/riscv/tt_atlantis.h create mode 100755 tests/functional/riscv64/test_tt_atlantis.py -- 2.53.0