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Fri, 8 May 2026 18:37:53 +0000 Received: from BY5PR12MB4179.namprd12.prod.outlook.com ([fe80::2036:e8b:9b3:f325]) by BY5PR12MB4179.namprd12.prod.outlook.com ([fe80::2036:e8b:9b3:f325%4]) with mapi id 15.20.9891.019; Fri, 8 May 2026 18:37:53 +0000 From: Tushar Dave To: qemu-devel@nongnu.org Cc: alwilliamson@nvidia.com, jgg@nvidia.com, skolothumtho@nvidia.com, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, marcel.apfelbaum@gmail.com, devel@edk2.groups.io Subject: [RFC PATCH 6/8] hw/pci: finalize bridge prefetch windows after BAR allocation Date: Fri, 8 May 2026 13:37:15 -0500 Message-Id: <20260508183717.193630-7-tdave@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260508183717.193630-1-tdave@nvidia.com> References: <20260508183717.193630-1-tdave@nvidia.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: BN9PR03CA0939.namprd03.prod.outlook.com (2603:10b6:408:108::14) To BY5PR12MB4179.namprd12.prod.outlook.com (2603:10b6:a03:211::8) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BY5PR12MB4179:EE_|DM4PR12MB6205:EE_ X-MS-Office365-Filtering-Correlation-Id: 929ce5f3-2add-4657-8224-08dead30ea64 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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envelope-from=tdave@nvidia.com; helo=CH1PR05CU001.outbound.protection.outlook.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.44, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 08 May 2026 16:42:45 -0400 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Add a final reconciliation pass to update bridge prefetch windows after all BARs have been assigned across all phases. This ensures bridge windows accurately reflect final BAR placement across all buses. SR-IOV virtual functions are not included when sizing bridge prefetch apertures and may require additional work. Signed-off-by: Tushar Dave --- hw/pci/pci-resource.c | 89 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/hw/pci/pci-resource.c b/hw/pci/pci-resource.c index e2d2adc7de..01db59c4af 100644 --- a/hw/pci/pci-resource.c +++ b/hw/pci/pci-resource.c @@ -190,6 +190,76 @@ static void pci_update_prefetch_window(PCIBus *bus, uint64_t base, uint64_t limi 4); } +static void pci_get_bridge_window(PCIBus *bus, void *opaque) +{ + PCIDevice *bridge = pci_bridge_get_device(bus); + PciAllocCfg *pci_res = (PciAllocCfg *)opaque; + + if (!bridge) { + pci_res->wbase = pci_res->mmio32_base; + pci_res->wlimit = pci_res->mmio32_base + pci_res->mmio32_size - 1; + pci_res->wbase64 = pci_res->mmio64_base; + pci_res->wlimit64 = pci_res->mmio64_base + pci_res->mmio64_size - 1; + } else { + pci_res->wbase = pci_bridge_get_base(bridge, PCI_BASE_ADDRESS_MEM_TYPE_32); + pci_res->wlimit = pci_bridge_get_limit(bridge, PCI_BASE_ADDRESS_MEM_TYPE_32); + pci_res->wbase64 = pci_bridge_get_base(bridge, PCI_BASE_ADDRESS_MEM_PREFETCH); + pci_res->wlimit64 = pci_bridge_get_limit(bridge, PCI_BASE_ADDRESS_MEM_PREFETCH); + } +} + +static void pci_collect_mmio64_window(PCIBus *bus, PCIDevice *dev, void *opaque) +{ + PciAllocCfg *pci_res = (PciAllocCfg *)opaque; + uint64_t rbase, rlimit; + uint32_t idx; + + for (idx = 0; idx < PCI_ROM_SLOT; idx++) { + PCIIORegion *res = &dev->io_regions[idx]; + + if (!res->size) { + continue; + } + rbase = res->addr; + rlimit = res->addr + res->size - 1; + /* Entire BAR must lie in the window; do not count partial overlap. */ + if (rbase < pci_res->wbase64 || rlimit > pci_res->wlimit64) { + continue; + } + pci_res->rbase = MIN(pci_res->rbase, rbase); + pci_res->rlimit = MAX(pci_res->rlimit, rlimit); + } + + if (IS_PCI_BRIDGE(dev)) { + rbase = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); + rlimit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); + + if ((rbase < pci_res->wbase64) || + (rbase > pci_res->wlimit64) || + (rlimit < pci_res->wbase64) || + (rlimit > pci_res->wlimit64)) { + return; + } + + pci_res->rbase = MIN(pci_res->rbase, rbase); + pci_res->rlimit = MAX(pci_res->rlimit, rlimit); + } +} + +static void pci_bus_update_prefetch_window(PCIBus *bus, void *opaque) +{ + PciAllocCfg *pci_res = (PciAllocCfg *)opaque; + pci_res->rbase = ~0; + pci_res->rlimit = 0; + + assert(pci_bridge_get_device(bus)); + pci_for_each_device_under_bus(bus, pci_collect_mmio64_window, pci_res); + + if (pci_res->rlimit > pci_res->rbase) { + pci_update_prefetch_window(bus, pci_res->rbase, pci_res->rlimit); + } +} + static inline bool is_64bit_pref_bar(PCIIORegion *r) { if (!r->size) { @@ -1004,6 +1074,25 @@ void pci_fixed_bar_allocator(PCIBus *root, const PciFixedBarMmioParams *mmio) /* Phase 3: allocate BARs for buses that have no fixed-BAR devices */ pci_for_each_bus(bus, pci_bus_phase3_allocate_no_fixed_bars, &pctx); + memset(pci_res, 0, sizeof(PciAllocCfg)); + pci_resource_init_from_mmio(pci_res, mmio); + + /* TODO: 32-bit MMIO/ROM adjustment */ + /* TODO: PIO assignment */ + /* TODO: 64-bit non-prefetchable */ + + /* Align bridge prefetch window with assigned BAR ranges */ + pci_get_bridge_window(bus, pci_res); + + QLIST_FOREACH(bus, &bus->child, sibling) { + pci_res->bus = bus; + /* Use the full mmio64 window */ + pci_res->wbase64 = pci_res->mmio64_base; + pci_res->wlimit64 = pci_res->mmio64_base + pci_res->mmio64_size - 1; + + pci_for_each_bus(bus, pci_bus_update_prefetch_window, pci_res); + } + /* Cleanup */ g_hash_table_destroy(pctx.had_fixed); fixed_claim_regions_reset(); -- 2.34.1