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From: sashiko-bot@kernel.org
To: Prabhakar <prabhakar.csengg@gmail.com>
Cc: krzk+dt@kernel.org, robh@kernel.org, conor+dt@kernel.org,
	devicetree@vger.kernel.org, wsa+renesas@sang-engineering.com
Subject: Re: [PATCH v2 1/4] dt-bindings: display: renesas,rzg2l-du: Add RZ/T2H and RZ/N2H support
Date: Fri, 08 May 2026 20:22:32 +0000	[thread overview]
Message-ID: <20260508202233.47B7DC2BCB0@smtp.kernel.org> (raw)
In-Reply-To: <20260508111744.771659-2-prabhakar.mahadev-lad.rj@bp.renesas.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The conditional constraints for renesas,r9a09g077-du fail to explicitly disallow port@1, permitting invalid device trees to silently pass validation.
--

commit cd9bf5724c5d57e0dd67fd27e0187153179b0578
Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

dt-bindings: display: renesas,rzg2l-du: Add RZ/T2H and RZ/N2H support

This commit documents the Display Unit (DU) support for the RZ/T2H and RZ/N2H
SoCs. It adds new compatible strings and updates the allOf constraints to
handle the SoCs' specific register differences and lack of reset control.

> diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> index 2cc66dcef870a..18776ac9e7c7e 100644
> --- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
[ ... ]
> @@ -95,7 +98,9 @@ allOf:
>        properties:
>          compatible:
>            contains:
> -            const: renesas,r9a07g043u-du
> +            enum:
> +              - renesas,r9a07g043u-du
> +              - renesas,r9a09g077-du
>      then:
>        properties:
>          ports:
> @@ -137,6 +142,17 @@ allOf:
>  
>            required:
>              - port@0

Should we also explicitly set port@1 to false here?

The base schema for 'ports' allows both 'port@0' and 'port@1' via the
patternProperty '^port@[0-1]$'. By not explicitly disallowing port@1 in this
conditional block for the single-port RZ/T2H DU variant, would a malformed
device tree containing an extra port@1 incorrectly pass schema validation?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260508111744.771659-1-prabhakar.mahadev-lad.rj@bp.renesas.com?part=1

  reply	other threads:[~2026-05-08 20:22 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-08 11:17 [PATCH v2 0/4] Add DU support for RZ/T2H and RZ/N2H SoCs Prabhakar
2026-05-08 11:17 ` [PATCH v2 1/4] dt-bindings: display: renesas, rzg2l-du: Add RZ/T2H and RZ/N2H support Prabhakar
2026-05-08 11:17   ` [PATCH v2 1/4] dt-bindings: display: renesas,rzg2l-du: " Prabhakar
2026-05-08 20:22   ` sashiko-bot [this message]
2026-05-12 12:34     ` Lad, Prabhakar
2026-05-08 11:17 ` [PATCH v2 2/4] drm: renesas: rz-du: Make DU reset control optional for RZ/T2H support Prabhakar
2026-05-08 11:17 ` [PATCH v2 3/4] drm: renesas: rz-du: Move mode_valid logic to per-SoC clock limits Prabhakar
2026-05-08 20:38   ` sashiko-bot
2026-05-08 11:17 ` [PATCH v2 4/4] drm: renesas: rz-du: Add support for RZ/T2H SoC Prabhakar

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