From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8F2930BF4F for ; Fri, 8 May 2026 23:26:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778282780; cv=none; b=VlWtuJs/c041DYEzQqttLXCvIoAtGUx2YjaX0uzQMj7qmecc7gUKKJQ/EeUwKTP4N/s207GDD6SWWEVm2axVJKkxgLpQp7W/Als7Fy1BJW120szn+trghkWHOXhSehjGkF7Hz+P7xf0Xzy1epgwZqdyhU9AZ35wiiVrMekPf3Jo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778282780; c=relaxed/simple; bh=GLsL7mMy0YYKQltGa+4I4uqaEt6ji4K6qjCRfSM/YkA=; h=From:Subject:To:Cc:In-Reply-To:References:Content-Type:Date: Message-Id; b=gy4H08BuAREqLCTLAYut+uwkjN2EISQ3IGb0tUeoF01jCGnRUJ477fKhnxQOHyrszOgPUBaopdW2kREj5W/+5+TOWB5rMHvtpm8RWL+NqgeJPs+tq/j/977Eda5PSORl+3acvVKZFW8INovksHFybL9gZ2LusXsrsRiHZ1WA9nI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cyDWCyu2; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cyDWCyu2" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2FD04C2BCB0; Fri, 8 May 2026 23:26:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778282780; bh=GLsL7mMy0YYKQltGa+4I4uqaEt6ji4K6qjCRfSM/YkA=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date:From; b=cyDWCyu2Ii9pmACua1GGn9q7y8bxYjfFnWyD4ONA1Vkr0w8eg4dqA7X6PoPOMTL6e 9MuerZ8fbZ4C+5th7zSP06xVFJp0RBma1+028qIs/L3IYEnRaCB0JN0C79GrKJ7cUQ 33fCKsT6nL1N+bIHt5TCgh/dfEycmPqofz0YQplSvGN16LM+K5k1C+Kr2/VZAOf15X v7OvhUZlo0ij7N7B2wqpsPnkURpa5vw5alMxhyjOdUTgFGqmeX+c7rIre5Hu2FZa0V K14LiuJyLTbG3jNh8Mz6EulP83ku0Ho4dewEP87+8VsH/+xeEy9qt1Pn/bcDrDBz44 NPrfRZpW98iuw== From: sashiko-bot@kernel.org Subject: Re: [PATCH v3 4/4] phy: qualcomm: qmp-combo: Add support for Hawi SoC Reply-To: sashiko@lists.linux.dev To: "Ronak Raheja" Cc: robh@kernel.org, krzk+dt@kernel.org, olteanv@gmail.com, devicetree@vger.kernel.org, vkoul@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org, linux-phy@lists.infradead.org In-Reply-To: <20260508213234.4643-5-ronak.raheja@oss.qualcomm.com> References: <20260508213234.4643-5-ronak.raheja@oss.qualcomm.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Date: Fri, 08 May 2026 23:26:19 +0000 Message-Id: <20260508232620.2FD04C2BCB0@smtp.kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Thank you for your contribution! Sashiko AI review found 2 potential issue(= s) to consider: - [High] Missing DP PHY function pointers in `hawi_usb3dpphy_cfg` lead to N= ULL pointer dereferences when the DP PHY is initialized. - [High] Valid register offset `0x00` causes the AON toggle hardware reset = override to be silently skipped. -- commit 39c99ec3129f1da7348c282db12eb565e967941d Author: Ronak Raheja phy: qualcomm: qmp-combo: Add support for Hawi SoC This commit adds support for the USB3-DP combo PHY found on the Hawi platform, introducing new V10 register layouts and the COM AON register module. > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qual= comm/phy-qcom-qmp-combo.c > index 93f1aa10d4008..53b709ea93d52 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c [ ... ] > @@ -2705,6 +2895,27 @@ static const struct qmp_phy_cfg x1e80100_usb3dpphy= _cfg =3D { > .regs =3D qmp_v6_n4_usb3phy_regs_layout, > }; > =20 > +static const struct qmp_phy_cfg hawi_usb3dpphy_cfg =3D { > + .offsets =3D &qmp_combo_offsets_v10, > + > + .serdes_tbl =3D hawi_usb3_serdes_tbl, > + .serdes_tbl_num =3D ARRAY_SIZE(hawi_usb3_serdes_tbl), > + .tx_tbl =3D hawi_usb3_tx_tbl, > + .tx_tbl_num =3D ARRAY_SIZE(hawi_usb3_tx_tbl), > + .rx_tbl =3D hawi_usb3_rx_tbl, > + .rx_tbl_num =3D ARRAY_SIZE(hawi_usb3_rx_tbl), > + .pcs_tbl =3D hawi_usb3_pcs_tbl, > + .pcs_tbl_num =3D ARRAY_SIZE(hawi_usb3_pcs_tbl), > + .pcs_usb_tbl =3D hawi_usb3_pcs_usb_tbl, > + .pcs_usb_tbl_num =3D ARRAY_SIZE(hawi_usb3_pcs_usb_tbl), > + > + .regs =3D qmp_v10_usb3phy_regs_layout, > + .reset_list =3D msm8996_usb3phy_reset_l, > + .num_resets =3D ARRAY_SIZE(msm8996_usb3phy_reset_l), > + .vreg_list =3D qmp_phy_vreg_l, > + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), > +}; Does this configuration miss the DP PHY function pointers?=20 Because this is a USB3-DP combo PHY, the driver unconditionally creates the= DP PHY. When a DisplayPort controller tries to initialize it, functions like qmp_combo_dp_init() and qmp_combo_dp_power_on() will unconditionally call cfg->dp_aux_init(qmp) and cfg->configure_dp_tx(qmp).=20 Without these pointers defined in hawi_usb3dpphy_cfg, will this lead to a N= ULL pointer dereference and a kernel panic upon DP PHY initialization? [ ... ] > @@ -3699,9 +3915,9 @@ static int qmp_combo_com_init(struct qmp_combo *qmp= , bool force) > SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); > =20 > /* override hardware control for reset of qmp phy */ > - if (pcs_aon && cfg->regs[QPHY_AON_TOGGLE_ENABLE]) { > - qphy_clrbits(pcs_aon, cfg->regs[QPHY_AON_TOGGLE_ENABLE], 0x1); > - qphy_clrbits(pcs_aon, cfg->regs[QPHY_DP_AON_TOGGLE_ENABLE], 0x1); > + if (aon_toggle && cfg->regs[QPHY_AON_TOGGLE_ENABLE]) { > + qphy_clrbits(aon_toggle, cfg->regs[QPHY_AON_TOGGLE_ENABLE], 0x1); > + qphy_clrbits(aon_toggle, cfg->regs[QPHY_DP_AON_TOGGLE_ENABLE], 0x1); > } Is it possible for the hardware reset override to be silently skipped here? The V10 register layout maps QPHY_AON_TOGGLE_ENABLE to QPHY_V10_COM_AON_USB3_AON_TOGGLE_ENABLE, which is defined as 0x00 in phy-qcom-qmp-com-aon-v10.h. Because 0x00 is a valid register offset but evaluates to false in C, the check for cfg->regs[QPHY_AON_TOGGLE_ENABLE] will fail. This would skip the qphy_clrbits() calls entirely, bypassing the necessary hardware reset overr= ide sequence and leaving the PHY in a broken state.=20 Could we use a different way to check if this register is supported by the layout without relying on the truthiness of the offset value? --=20 Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20260508213234.4643= -1-ronak.raheja@oss.qualcomm.com?part=3D4 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 76D44CD3445 for ; Fri, 8 May 2026 23:26:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Reply-To:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date: References:In-Reply-To:Cc:To:Subject:From:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=TZwEVE0QIy75fzut58mVd/4W5+bnUnoTr08f8E7I4yc=; b=oRtToVu7LF1dIa Ek/Pi+lrqOKRnFBitUU82w8yAbMllM2MmzSYcVeCyrxJPcHNUpcQ/4aaaD+8hxPaaD3HLa4jQwSZy Q/5yEo8QuwmqWjN0oTIwGQxkN0rOO5P1bMx7czuHddeDkLUQ95iRxNafcFyFBos6YLHyCnT7vNgEq DhEmTw1R+GEi/Bfpl81rsvP3KwuKt8iQ+5tKcfedm4Z0EH/wfAeiczB4tu+NGjFgYoJ2nO3lkDruf 5zdSGdWWYdGWVNYjdtnJPcr6Fdb8gm4csMdc3LYdrtOjJcr3up46pRriAGIY8AntUeWEiNn2RBi+k Kl/cENI/AyhKjGsd2m2g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wLUaN-00000007kYQ-0tfA; Fri, 08 May 2026 23:26:24 +0000 Received: from tor.source.kernel.org ([172.105.4.254]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wLUaL-00000007kXt-2nO6 for linux-phy@lists.infradead.org; Fri, 08 May 2026 23:26:21 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id CBF206057A; Fri, 8 May 2026 23:26:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2FD04C2BCB0; Fri, 8 May 2026 23:26:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778282780; bh=GLsL7mMy0YYKQltGa+4I4uqaEt6ji4K6qjCRfSM/YkA=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date:From; b=cyDWCyu2Ii9pmACua1GGn9q7y8bxYjfFnWyD4ONA1Vkr0w8eg4dqA7X6PoPOMTL6e 9MuerZ8fbZ4C+5th7zSP06xVFJp0RBma1+028qIs/L3IYEnRaCB0JN0C79GrKJ7cUQ 33fCKsT6nL1N+bIHt5TCgh/dfEycmPqofz0YQplSvGN16LM+K5k1C+Kr2/VZAOf15X v7OvhUZlo0ij7N7B2wqpsPnkURpa5vw5alMxhyjOdUTgFGqmeX+c7rIre5Hu2FZa0V K14LiuJyLTbG3jNh8Mz6EulP83ku0Ho4dewEP87+8VsH/+xeEy9qt1Pn/bcDrDBz44 NPrfRZpW98iuw== From: sashiko-bot@kernel.org Subject: Re: [PATCH v3 4/4] phy: qualcomm: qmp-combo: Add support for Hawi SoC To: "Ronak Raheja" Cc: robh@kernel.org, krzk+dt@kernel.org, olteanv@gmail.com, devicetree@vger.kernel.org, vkoul@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org, linux-phy@lists.infradead.org In-Reply-To: <20260508213234.4643-5-ronak.raheja@oss.qualcomm.com> References: <20260508213234.4643-5-ronak.raheja@oss.qualcomm.com> Date: Fri, 08 May 2026 23:26:19 +0000 Message-Id: <20260508232620.2FD04C2BCB0@smtp.kernel.org> X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: sashiko@lists.linux.dev MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org VGhhbmsgeW91IGZvciB5b3VyIGNvbnRyaWJ1dGlvbiEgU2FzaGlrbyBBSSByZXZpZXcgZm91bmQg MiBwb3RlbnRpYWwgaXNzdWUocykgdG8gY29uc2lkZXI6Ci0gW0hpZ2hdIE1pc3NpbmcgRFAgUEhZ IGZ1bmN0aW9uIHBvaW50ZXJzIGluIGBoYXdpX3VzYjNkcHBoeV9jZmdgIGxlYWQgdG8gTlVMTCBw b2ludGVyIGRlcmVmZXJlbmNlcyB3aGVuIHRoZSBEUCBQSFkgaXMgaW5pdGlhbGl6ZWQuCi0gW0hp Z2hdIFZhbGlkIHJlZ2lzdGVyIG9mZnNldCBgMHgwMGAgY2F1c2VzIHRoZSBBT04gdG9nZ2xlIGhh cmR3YXJlIHJlc2V0IG92ZXJyaWRlIHRvIGJlIHNpbGVudGx5IHNraXBwZWQuCi0tCgpjb21taXQg MzljOTllYzMxMjlmMWRhNzM0OGMyODJkYjEyZWI1NjVlOTY3OTQxZApBdXRob3I6IFJvbmFrIFJh aGVqYSA8cm9uYWsucmFoZWphQG9zcy5xdWFsY29tbS5jb20+CgpwaHk6IHF1YWxjb21tOiBxbXAt Y29tYm86IEFkZCBzdXBwb3J0IGZvciBIYXdpIFNvQwoKVGhpcyBjb21taXQgYWRkcyBzdXBwb3J0 IGZvciB0aGUgVVNCMy1EUCBjb21ibyBQSFkgZm91bmQgb24gdGhlIEhhd2kKcGxhdGZvcm0sIGlu dHJvZHVjaW5nIG5ldyBWMTAgcmVnaXN0ZXIgbGF5b3V0cyBhbmQgdGhlIENPTSBBT04gcmVnaXN0 ZXIKbW9kdWxlLgoKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9waHkvcXVhbGNvbW0vcGh5LXFjb20t cW1wLWNvbWJvLmMgYi9kcml2ZXJzL3BoeS9xdWFsY29tbS9waHktcWNvbS1xbXAtY29tYm8uYwo+ IGluZGV4IDkzZjFhYTEwZDQwMDguLjUzYjcwOWVhOTNkNTIgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVy cy9waHkvcXVhbGNvbW0vcGh5LXFjb20tcW1wLWNvbWJvLmMKPiArKysgYi9kcml2ZXJzL3BoeS9x dWFsY29tbS9waHktcWNvbS1xbXAtY29tYm8uYwpbIC4uLiBdCj4gQEAgLTI3MDUsNiArMjg5NSwy NyBAQCBzdGF0aWMgY29uc3Qgc3RydWN0IHFtcF9waHlfY2ZnIHgxZTgwMTAwX3VzYjNkcHBoeV9j ZmcgPSB7Cj4gIAkucmVncwkJCT0gcW1wX3Y2X240X3VzYjNwaHlfcmVnc19sYXlvdXQsCj4gIH07 Cj4gIAo+ICtzdGF0aWMgY29uc3Qgc3RydWN0IHFtcF9waHlfY2ZnIGhhd2lfdXNiM2RwcGh5X2Nm ZyA9IHsKPiArCS5vZmZzZXRzCQk9ICZxbXBfY29tYm9fb2Zmc2V0c192MTAsCj4gKwo+ICsJLnNl cmRlc190YmwJCT0gaGF3aV91c2IzX3NlcmRlc190YmwsCj4gKwkuc2VyZGVzX3RibF9udW0JCT0g QVJSQVlfU0laRShoYXdpX3VzYjNfc2VyZGVzX3RibCksCj4gKwkudHhfdGJsCQkJPSBoYXdpX3Vz YjNfdHhfdGJsLAo+ICsJLnR4X3RibF9udW0JCT0gQVJSQVlfU0laRShoYXdpX3VzYjNfdHhfdGJs KSwKPiArCS5yeF90YmwJCQk9IGhhd2lfdXNiM19yeF90YmwsCj4gKwkucnhfdGJsX251bQkJPSBB UlJBWV9TSVpFKGhhd2lfdXNiM19yeF90YmwpLAo+ICsJLnBjc190YmwJCT0gaGF3aV91c2IzX3Bj c190YmwsCj4gKwkucGNzX3RibF9udW0JCT0gQVJSQVlfU0laRShoYXdpX3VzYjNfcGNzX3RibCks Cj4gKwkucGNzX3VzYl90YmwJCT0gaGF3aV91c2IzX3Bjc191c2JfdGJsLAo+ICsJLnBjc191c2Jf dGJsX251bQk9IEFSUkFZX1NJWkUoaGF3aV91c2IzX3Bjc191c2JfdGJsKSwKPiArCj4gKwkucmVn cwkJCT0gcW1wX3YxMF91c2IzcGh5X3JlZ3NfbGF5b3V0LAo+ICsJLnJlc2V0X2xpc3QJCT0gbXNt ODk5Nl91c2IzcGh5X3Jlc2V0X2wsCj4gKwkubnVtX3Jlc2V0cwkJPSBBUlJBWV9TSVpFKG1zbTg5 OTZfdXNiM3BoeV9yZXNldF9sKSwKPiArCS52cmVnX2xpc3QJCT0gcW1wX3BoeV92cmVnX2wsCj4g KwkubnVtX3ZyZWdzCQk9IEFSUkFZX1NJWkUocW1wX3BoeV92cmVnX2wpLAo+ICt9OwoKRG9lcyB0 aGlzIGNvbmZpZ3VyYXRpb24gbWlzcyB0aGUgRFAgUEhZIGZ1bmN0aW9uIHBvaW50ZXJzPyAKCkJl Y2F1c2UgdGhpcyBpcyBhIFVTQjMtRFAgY29tYm8gUEhZLCB0aGUgZHJpdmVyIHVuY29uZGl0aW9u YWxseSBjcmVhdGVzIHRoZSBEUApQSFkuIFdoZW4gYSBEaXNwbGF5UG9ydCBjb250cm9sbGVyIHRy aWVzIHRvIGluaXRpYWxpemUgaXQsIGZ1bmN0aW9ucyBsaWtlCnFtcF9jb21ib19kcF9pbml0KCkg YW5kIHFtcF9jb21ib19kcF9wb3dlcl9vbigpIHdpbGwgdW5jb25kaXRpb25hbGx5IGNhbGwKY2Zn LT5kcF9hdXhfaW5pdChxbXApIGFuZCBjZmctPmNvbmZpZ3VyZV9kcF90eChxbXApLiAKCldpdGhv dXQgdGhlc2UgcG9pbnRlcnMgZGVmaW5lZCBpbiBoYXdpX3VzYjNkcHBoeV9jZmcsIHdpbGwgdGhp cyBsZWFkIHRvIGEgTlVMTApwb2ludGVyIGRlcmVmZXJlbmNlIGFuZCBhIGtlcm5lbCBwYW5pYyB1 cG9uIERQIFBIWSBpbml0aWFsaXphdGlvbj8KClsgLi4uIF0KPiBAQCAtMzY5OSw5ICszOTE1LDkg QEAgc3RhdGljIGludCBxbXBfY29tYm9fY29tX2luaXQoc3RydWN0IHFtcF9jb21ibyAqcW1wLCBi b29sIGZvcmNlKQo+ICAJCQlTV19VU0IzUEhZX1JFU0VUX01VWCB8IFNXX1VTQjNQSFlfUkVTRVQp Owo+ICAKPiAgCS8qIG92ZXJyaWRlIGhhcmR3YXJlIGNvbnRyb2wgZm9yIHJlc2V0IG9mIHFtcCBw aHkgKi8KPiAtCWlmIChwY3NfYW9uICYmIGNmZy0+cmVnc1tRUEhZX0FPTl9UT0dHTEVfRU5BQkxF XSkgewo+IC0JCXFwaHlfY2xyYml0cyhwY3NfYW9uLCBjZmctPnJlZ3NbUVBIWV9BT05fVE9HR0xF X0VOQUJMRV0sIDB4MSk7Cj4gLQkJcXBoeV9jbHJiaXRzKHBjc19hb24sIGNmZy0+cmVnc1tRUEhZ X0RQX0FPTl9UT0dHTEVfRU5BQkxFXSwgMHgxKTsKPiArCWlmIChhb25fdG9nZ2xlICYmIGNmZy0+ cmVnc1tRUEhZX0FPTl9UT0dHTEVfRU5BQkxFXSkgewo+ICsJCXFwaHlfY2xyYml0cyhhb25fdG9n Z2xlLCBjZmctPnJlZ3NbUVBIWV9BT05fVE9HR0xFX0VOQUJMRV0sIDB4MSk7Cj4gKwkJcXBoeV9j bHJiaXRzKGFvbl90b2dnbGUsIGNmZy0+cmVnc1tRUEhZX0RQX0FPTl9UT0dHTEVfRU5BQkxFXSwg MHgxKTsKPiAgCX0KCklzIGl0IHBvc3NpYmxlIGZvciB0aGUgaGFyZHdhcmUgcmVzZXQgb3ZlcnJp ZGUgdG8gYmUgc2lsZW50bHkgc2tpcHBlZCBoZXJlPwoKVGhlIFYxMCByZWdpc3RlciBsYXlvdXQg bWFwcyBRUEhZX0FPTl9UT0dHTEVfRU5BQkxFIHRvClFQSFlfVjEwX0NPTV9BT05fVVNCM19BT05f VE9HR0xFX0VOQUJMRSwgd2hpY2ggaXMgZGVmaW5lZCBhcyAweDAwIGluCnBoeS1xY29tLXFtcC1j b20tYW9uLXYxMC5oLgoKQmVjYXVzZSAweDAwIGlzIGEgdmFsaWQgcmVnaXN0ZXIgb2Zmc2V0IGJ1 dCBldmFsdWF0ZXMgdG8gZmFsc2UgaW4gQywgdGhlCmNoZWNrIGZvciBjZmctPnJlZ3NbUVBIWV9B T05fVE9HR0xFX0VOQUJMRV0gd2lsbCBmYWlsLiBUaGlzIHdvdWxkIHNraXAgdGhlCnFwaHlfY2xy Yml0cygpIGNhbGxzIGVudGlyZWx5LCBieXBhc3NpbmcgdGhlIG5lY2Vzc2FyeSBoYXJkd2FyZSBy ZXNldCBvdmVycmlkZQpzZXF1ZW5jZSBhbmQgbGVhdmluZyB0aGUgUEhZIGluIGEgYnJva2VuIHN0 YXRlLiAKCkNvdWxkIHdlIHVzZSBhIGRpZmZlcmVudCB3YXkgdG8gY2hlY2sgaWYgdGhpcyByZWdp c3RlciBpcyBzdXBwb3J0ZWQgYnkgdGhlCmxheW91dCB3aXRob3V0IHJlbHlpbmcgb24gdGhlIHRy dXRoaW5lc3Mgb2YgdGhlIG9mZnNldCB2YWx1ZT8KCi0tIApTYXNoaWtvIEFJIHJldmlldyDCtyBo dHRwczovL3Nhc2hpa28uZGV2LyMvcGF0Y2hzZXQvMjAyNjA1MDgyMTMyMzQuNDY0My0xLXJvbmFr LnJhaGVqYUBvc3MucXVhbGNvbW0uY29tP3BhcnQ9NAoKLS0gCmxpbnV4LXBoeSBtYWlsaW5nIGxp c3QKbGludXgtcGh5QGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cHM6Ly9saXN0cy5pbmZyYWRlYWQu b3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtcGh5Cg==