From: sashiko-bot@kernel.org
To: "Richard Zhu" <hongxing.zhu@nxp.com>
Cc: Frank.Li@kernel.org, krzk+dt@kernel.org,
devicetree@vger.kernel.org, conor+dt@kernel.org,
imx@lists.linux.dev, robh@kernel.org
Subject: Re: [PATCH v2] arm64: dts: imx95: Increase PCIe outbound address space to 2GB
Date: Sat, 09 May 2026 02:18:55 +0000 [thread overview]
Message-ID: <20260509021855.D03FDC2BCB0@smtp.kernel.org> (raw)
In-Reply-To: <20260509020440.3219767-1-hongxing.zhu@nxp.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The expanded 2GB PCIe outbound memory window cannot allocate a 2GB BAR and restricts 1GB BAR allocations due to PCI address alignment constraints.
--
commit 6da3bf3dfff2671c469eeafa736ee204651d7b67
Author: Richard Zhu <hongxing.zhu@nxp.com>
arm64: dts: imx95: Increase PCIe outbound address space to 2GB
This commit expands the PCIe outbound memory region to 2GB to support
devices requiring larger address spaces.
> diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
> --- a/arch/arm64/boot/dts/freescale/imx95.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
> @@ -1846,7 +1846,7 @@ pcie0: pcie@4c300000 {
> <0 0x4c340000 0 0x4000>;
> reg-names = "dbi", "config", "atu", "app";
> ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>,
> - <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>;
> + <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x80000000>;
With this update, the PCI address window starts at 0x10000000 and has a
size of 0x80000000.
Because PCI specifications require a Base Address Register to be naturally
aligned to its size, a 2GB allocation would have to start at 0x80000000.
Since a 2GB allocation starting at 0x80000000 ends at 0xffffffff, does
this exceed the top of the defined window at 0x8fffffff?
It seems like this would prevent allocating a full 2GB address space.
[ ... ]
> @@ -1921,7 +1921,7 @@ pcie1: pcie@4c380000 {
> <0 0x4c3c0000 0 0x4000>;
> reg-names = "dbi", "config", "atu", "app";
> ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>,
> - <0x82000000 0 0x10000000 0xa 0x10000000 0 0x10000000>;
> + <0x82000000 0 0x10000000 0xa 0x10000000 0 0x80000000>;
This appears to have the same alignment restriction that would prevent a
2GB allocation.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260509020440.3219767-1-hongxing.zhu@nxp.com?part=1
prev parent reply other threads:[~2026-05-09 2:18 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-09 2:04 [PATCH v2] arm64: dts: imx95: Increase PCIe outbound address space to 2GB Richard Zhu
2026-05-09 2:18 ` sashiko-bot [this message]
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