[asahilinux:bits/171-dptxphy 1/1] drivers/phy/apple/dptx.c:98 dptx_phy_set_active_lane_count() warn: inconsistent indenting

[kernel test robot <lkp@intel.com>]

tree:   https://github.com/AsahiLinux/linux bits/171-dptxphy
head:   bd8e7fa49e0d5ad013b1089ee5305074823b1382
commit: bd8e7fa49e0d5ad013b1089ee5305074823b1382 [1/1] phy: apple: Add DP TX phy driver
config: um-randconfig-r072-20260509 (https://download.01.org/0day-ci/archive/20260510/202605100948.xvUvuQAM-lkp@intel.com/config)
compiler: clang version 23.0.0git (https://github.com/llvm/llvm-project 5bac06718f502014fade905512f1d26d578a18f3)
smatch: v0.5.0-9065-ge9cc34fd

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202605100948.xvUvuQAM-lkp@intel.com/

smatch warnings:
drivers/phy/apple/dptx.c:98 dptx_phy_set_active_lane_count() warn: inconsistent indenting
drivers/phy/apple/dptx.c:328 dptx_phy_set_link_rate() warn: inconsistent indenting

vim +98 drivers/phy/apple/dptx.c

    79	
    80	
    81	static int dptx_phy_set_active_lane_count(struct apple_dptx_phy *phy, u32 num_lanes)
    82	{
    83		u32 l, ctrl;
    84	
    85		dev_dbg(phy->dev, "set_active_lane_count(%u)\n", num_lanes);
    86	
    87		if (num_lanes == 3 || num_lanes > DPTX_MAX_LANES)
    88			return -1;
    89	
    90		ctrl = readl(phy->regs.dptx + 0x4000);
    91		writel(ctrl, phy->regs.dptx + 0x4000);
    92	
    93		for (l = 0; l < num_lanes; l++) {
    94			u64 offset = 0x5000 + 0x1000 * l;
    95			readl(phy->regs.dptx + offset);
    96			writel(0x100, phy->regs.dptx + offset);
    97	    }
  > 98	    for (; l < DPTX_MAX_LANES; l++) {
    99	        u64 offset = 0x5000 + 0x1000 * l;
   100		readl(phy->regs.dptx + offset);
   101		writel(0x300, phy->regs.dptx + offset);
   102	    }
   103	    for (l = 0; l < num_lanes; l++) {
   104	        u64 offset = 0x5000 + 0x1000 * l;
   105		readl(phy->regs.dptx + offset);
   106		writel(0x0, phy->regs.dptx + offset);
   107	    }
   108	    for (; l < DPTX_MAX_LANES; l++) {
   109	        u64 offset = 0x5000 + 0x1000 * l;
   110		readl(phy->regs.dptx + offset);
   111		writel(0x300, phy->regs.dptx + offset);
   112	    }
   113	
   114	    if (num_lanes > 0) {
   115		// clear32(phy->regs.dptx + 0x4000, 0x4000000);
   116		ctrl = readl(phy->regs.dptx + 0x4000);
   117		ctrl &= ~0x4000000;
   118		writel(ctrl, phy->regs.dptx + 0x4000);
   119	    }
   120	    phy->active_lanes = num_lanes;
   121	
   122	    return 0;
   123	}
   124	

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