From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D03B3DB645 for ; Mon, 11 May 2026 13:16:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778505413; cv=none; b=KGLD+aZZYbcteOVWjfK23ADVTk78DVWcaZMcp3Co7QXAD1xa2rnoQzE+bQb1l3rFDRS71pF1+IuGxj1J3x24ca3c5bHr6UJYztt8CLplgmVXt3Mhi8cd1IHXWxTLz24J4xv9B++zV4sH7qVL8duEUdss/ye5HligOqHtuq1Nxcs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778505413; c=relaxed/simple; bh=PiOqxEukuNZT1rJjTyc7+Yxyn2mjSXln405hbufqHO8=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=C9XU///EmdGE/mTD+qm2TFWDQdfZqHX6PXS85y8SuqND7isaNYQeOdg3LzXI/i6iO3S8KSvh8h/GxOJOgFonA8A4rljZvdVS1G0Qcf+eBAahgKtJjmOW2tZDEamin2OELNj8V12/iI+LdAYocbSlGhCNig3QPExOA4esDSvkeT0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=M93R7Z8p; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="M93R7Z8p" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id A026826F93; Mon, 11 May 2026 15:16:41 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id 25CJDAQ2kAgI; Mon, 11 May 2026 15:16:41 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1778505401; bh=PiOqxEukuNZT1rJjTyc7+Yxyn2mjSXln405hbufqHO8=; h=From:To:Cc:Subject:Date; b=M93R7Z8p2pVfkOdTXhI5qJRIy1VCmjy63ritWixpKbLztnKeK4U1EU/TG+SE1mfpq qdIA70QmfQbP9DZMzArkQoODoAZ0JeKOz7JcaKd+JpoNtAyPV8ODqBFB31ZlHg2Ogr BAi5SOQKqYjmEz4z5U5Dl81n6HSGYPePF8weDF/Xyci06QUZhgCNEBddf+kIVqmKaP +0Le1Oa7azBRA8EiUoZcdaGtnSm+CpHtiSDXEbjIVy2dOcKSZFQJ9LqyQJXt8GWWEs 9rTezwhQtfYxaiPGzipDnJ1WVT9+TM7jyUIEDNabdSQ1GYw5hJvp1N8heYnvYyjVkx Ejd1CNHDSnAcQ== From: Rustam Adilov To: Daniel Lezcano , Thomas Gleixner , linux-kernel@vger.kernel.org Cc: Rustam Adilov Subject: [PATCH] clocksource: rtl-otto: Change driver to use __raw reads and writes Date: Mon, 11 May 2026 18:15:20 +0500 Message-ID: <20260511131520.98420-1-adilov@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit As it stands, the driver uses ioread32 and iowrite32 for register access and it works fine. However this stops working when the SWAP_IO_SPACE config is enabled as this drivers expects ioread32 and iowrite32 to be in native endian (that is big endian for currently supported SoCs). RTL9607C is a big endian MIPS SoC that has identical timer as the already supported chips but needs to have SWAP_IO_SPACE to have a functioning little endian USB host. Fix this by replacing all instances of ioread32 and iowrite32 with __raw_readl and __raw_writel variants. Since they essentially do the same register access, this shouldn't affect anything on other machines. Signed-off-by: Rustam Adilov --- drivers/clocksource/timer-rtl-otto.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/clocksource/timer-rtl-otto.c b/drivers/clocksource/timer-rtl-otto.c index 6113d2fdd4de..bcb449ef0481 100644 --- a/drivers/clocksource/timer-rtl-otto.c +++ b/drivers/clocksource/timer-rtl-otto.c @@ -56,37 +56,37 @@ struct rttm_cs { /* Simple internal register functions */ static inline unsigned int rttm_get_counter(void __iomem *base) { - return ioread32(base + RTTM_CNT); + return __raw_readl(base + RTTM_CNT); } static inline void rttm_set_period(void __iomem *base, unsigned int period) { - iowrite32(period, base + RTTM_DATA); + __raw_writel(period, base + RTTM_DATA); } static inline void rttm_disable_timer(void __iomem *base) { - iowrite32(0, base + RTTM_CTRL); + __raw_writel(0, base + RTTM_CTRL); } static inline void rttm_enable_timer(void __iomem *base, u32 mode, u32 divisor) { - iowrite32(RTTM_CTRL_ENABLE | mode | divisor, base + RTTM_CTRL); + __raw_writel(RTTM_CTRL_ENABLE | mode | divisor, base + RTTM_CTRL); } static inline void rttm_ack_irq(void __iomem *base) { - iowrite32(ioread32(base + RTTM_INT) | RTTM_INT_PENDING, base + RTTM_INT); + __raw_writel(__raw_readl(base + RTTM_INT) | RTTM_INT_PENDING, base + RTTM_INT); } static inline void rttm_enable_irq(void __iomem *base) { - iowrite32(RTTM_INT_ENABLE, base + RTTM_INT); + __raw_writel(RTTM_INT_ENABLE, base + RTTM_INT); } static inline void rttm_disable_irq(void __iomem *base) { - iowrite32(0, base + RTTM_INT); + __raw_writel(0, base + RTTM_INT); } /* Aggregated control functions for kernel clock framework */ -- 2.54.0