From: Narayana Murty N <nnmlinux@linux.ibm.com>
To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Cc: npiggin@gmail.com, harshpb@linux.ibm.com, mahesh@linux.ibm.com,
ganeshgr@linux.ibm.com, sbhat@linux.ibm.com,
vaibhav@linux.ibm.com, anushree.mathur@linux.vnet.ibm.com
Subject: [PATCH 2/6] ppc/spapr: Add ibm,errinjct RTAS call handler
Date: Tue, 12 May 2026 12:41:07 +0530 [thread overview]
Message-ID: <20260512071112.9675-3-nnmlinux@linux.ibm.com> (raw)
In-Reply-To: <20260512071112.9675-1-nnmlinux@linux.ibm.com>
Implements the 'ibm,errinjct' RTAS call for PHB-level PCI error injection
via firmware. This handler decodes the RTAS parameter buffer, validates
arguments, and delegates the injection to the backend.
The patch includes:
- 'rtas_ibm_errinjct()' handler implementation
- Registration of 'RTAS_IBM_ERRINJCT' token
- RTAS error codes for result reporting
- Helper macros used exclusively in RTAS code path
Enables guest-initiated error injection for improved test coverage and
diagnostics in EEH emulation flows.
Signed-off-by: Narayana Murty N <nnmlinux@linux.ibm.com>
---
hw/ppc/spapr_pci.c | 153 +++++++++++++++++++++++++++++++++++++++++
include/hw/ppc/spapr.h | 6 +-
2 files changed, 158 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index c1d4b7806e..82de04186e 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -704,6 +704,156 @@ param_error_exit:
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
}
+static int parse_and_verify_recovered_special_event(target_ulong param_buf,
+ uint64_t *addr) {
+ uint32_t mode = rtas_ld(param_buf, 0);
+ if (mode != EEH_ERR_EVENT_MODE_MIN && mode != EEH_ERR_EVENT_MODE_MAX) {
+ return RTAS_OUT_PARAM_ERROR;
+ }
+ *addr = ((uint64_t)mode) << 32;
+ qemu_log("RTAS: recovered-special-event: mode=%u\n", mode);
+ return RTAS_OUT_SUCCESS;
+}
+
+static int parse_and_verify_corrupted_page(target_ulong param_buf,
+ uint64_t *addr) {
+ *addr = ((uint64_t)rtas_ld(param_buf, 0) << 32) | rtas_ld(param_buf, 1);
+ qemu_log("RTAS: corrupted-page: addr=0x%lx\n", *addr);
+ return (*addr) ? RTAS_OUT_SUCCESS : RTAS_OUT_PARAM_ERROR;
+}
+
+static int parse_and_verify_ioa_bus_error(target_ulong param_buf,
+ bool is_64bit,
+ uint64_t *addr, uint64_t *mask,
+ uint64_t *buid, uint32_t *func)
+{
+ if (is_64bit) {
+ *addr = ((uint64_t)rtas_ld(param_buf, 0) << 32) | rtas_ld(param_buf, 1);
+ *mask = ((uint64_t)rtas_ld(param_buf, 2) << 32) | rtas_ld(param_buf, 3);
+ *buid = ((uint64_t)rtas_ld(param_buf, 5) << 32) | rtas_ld(param_buf, 6);
+ *func = rtas_ld(param_buf, 7);
+ } else {
+ *addr = rtas_ld(param_buf, 0);
+ *mask = rtas_ld(param_buf, 1);
+ *buid = ((uint64_t)rtas_ld(param_buf, 3) << 32) | rtas_ld(param_buf, 4);
+ *func = rtas_ld(param_buf, 5);
+ }
+
+ return RTAS_OUT_SUCCESS;
+}
+
+static int parse_and_verify_corrupted_dcache(target_ulong param_buf,
+ uint64_t *addr)
+{
+ uint32_t action = rtas_ld(param_buf, 0);
+ uint32_t nature = rtas_ld(param_buf, 1);
+ *addr = ((uint64_t)action << 32) | nature;
+
+ return (action <= 2 && nature <= 2) ? RTAS_OUT_SUCCESS
+ : RTAS_OUT_PARAM_ERROR;
+}
+
+static int parse_and_verify_corrupted_icache(target_ulong param_buf,
+ uint64_t *addr)
+{
+ uint32_t action = rtas_ld(param_buf, 0);
+ uint32_t nature = rtas_ld(param_buf, 1);
+ *addr = ((uint64_t)action << 32) | nature;
+
+ return (action <= 3 && nature <= 2) ? RTAS_OUT_SUCCESS
+ : RTAS_OUT_PARAM_ERROR;
+}
+
+static int parse_and_verify_corrupted_tlb(target_ulong param_buf,
+ uint64_t *addr)
+{
+ uint32_t nature = rtas_ld(param_buf, 0);
+ *addr = ((uint64_t)nature << 32);
+
+ return (nature <= 2) ? RTAS_OUT_SUCCESS : RTAS_OUT_PARAM_ERROR;
+}
+
+static void rtas_ibm_errinjct(PowerPCCPU *cpu, SpaprMachineState *spapr,
+ uint32_t token, uint32_t nargs,
+ target_ulong args, uint32_t nret,
+ target_ulong rets)
+{
+ SpaprPhbState *sphb;
+ target_ulong param_buf;
+ uint64_t addr = 0, mask = 0, buid = 0;
+ uint32_t func = 0;
+ uint32_t type, o_token;
+ int ret = -1;
+
+ if ((nargs != 3) || (nret != 1)) {
+ goto param_error_exit;
+ }
+
+ type = rtas_ld(args, 0);
+ o_token = rtas_ld(args, 1);
+ param_buf = rtas_ld(args, 2);
+
+ if (o_token != spapr->errinjct_token) {
+ goto param_error_exit;
+ }
+
+ sphb = QLIST_FIRST(&spapr->phbs);
+ if (!sphb) {
+ goto param_error_exit;
+ }
+
+ switch (type) {
+ case RTAS_ERR_TYPE_IOA_BUS_ERROR:
+ ret = parse_and_verify_ioa_bus_error(param_buf, false, &addr,
+ &mask, &buid, &func);
+ break;
+ case RTAS_ERR_TYPE_IOA_BUS_ERROR_64:
+ ret = parse_and_verify_ioa_bus_error(param_buf, true, &addr,
+ &mask, &buid, &func);
+ break;
+ case RTAS_ERR_TYPE_CORRUPTED_PAGE:
+ ret = parse_and_verify_corrupted_page(param_buf, &addr);
+ break;
+ case RTAS_ERR_TYPE_RECOVERED_SPECIAL_EVENT:
+ ret = parse_and_verify_recovered_special_event(param_buf, &addr);
+ break;
+ case RTAS_ERR_TYPE_CORRUPTED_DCACHE_START:
+ case RTAS_ERR_TYPE_CORRUPTED_DCACHE_END:
+ ret = parse_and_verify_corrupted_dcache(param_buf, &addr);
+ mask = 0;
+ break;
+ case RTAS_ERR_TYPE_CORRUPTED_ICACHE_START:
+ case RTAS_ERR_TYPE_CORRUPTED_ICACHE_END:
+ ret = parse_and_verify_corrupted_icache(param_buf, &addr);
+ mask = 0;
+ break;
+ case RTAS_ERR_TYPE_CORRUPTED_TLB_START:
+ case RTAS_ERR_TYPE_CORRUPTED_TLB_END:
+ ret = parse_and_verify_corrupted_tlb(param_buf, &addr);
+ mask = 0;
+ break;
+ default:
+ ret = RTAS_OUT_PARAM_ERROR;
+ break;
+ }
+
+ if (ret != RTAS_OUT_SUCCESS) {
+ goto param_error_exit;
+ }
+
+ ret = spapr_phb_vfio_errinjct(sphb, func, addr, mask, type);
+ if (ret < 0) {
+ rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
+ return;
+ }
+
+ rtas_st(rets, 0, RTAS_OUT_SUCCESS);
+ return;
+
+param_error_exit:
+ rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
+}
+
static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
{
/*
@@ -2380,6 +2530,9 @@ void spapr_pci_rtas_init(void)
spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL,
"ibm,slot-error-detail",
rtas_ibm_slot_error_detail);
+ spapr_rtas_register(RTAS_IBM_ERRINJCT,
+ "ibm,errinjct",
+ rtas_ibm_errinjct);
}
static void spapr_pci_register_types(void)
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index fadb7cf7d9..512dd038ec 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -706,6 +706,9 @@ void push_sregs_to_kvm_pr(SpaprMachineState *spapr);
#define EEH_ERR_FUNC_DMA_WR_TARGET 19
#define EEH_ERR_FUNC_MAX EEH_ERR_FUNC_DMA_WR_TARGET
+#define EEH_ERR_EVENT_MODE_MIN 1
+#define EEH_ERR_EVENT_MODE_MAX 2
+
/* RTAS PCI Error Injection Token Types */
enum rtas_err_type {
RTAS_ERR_TYPE_FATAL = 0x1,
@@ -808,8 +811,9 @@ enum rtas_err_type {
#define RTAS_IBM_NMI_REGISTER (RTAS_TOKEN_BASE + 0x2B)
#define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C)
#define RTAS_CONFIGURE_KERNEL_DUMP (RTAS_TOKEN_BASE + 0x2D)
+#define RTAS_IBM_ERRINJCT (RTAS_TOKEN_BASE + 0x2E)
-#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2E)
+#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2F)
/* RTAS ibm,get-system-parameter token values */
#define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20
--
2.54.0
next prev parent reply other threads:[~2026-05-12 7:12 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-12 7:11 [PATCH 0/6] ppc/spapr: Add RTAS error injection support for VFIO EEH Narayana Murty N
2026-05-12 7:11 ` [PATCH 1/6] ppc/spapr: Add VFIO EEH error injection backend Narayana Murty N
2026-05-12 7:11 ` Narayana Murty N [this message]
2026-05-12 7:11 ` [PATCH 3/6] ppc/spapr: Add support for 'ibm, open-errinjct' and 'ibm, close-errinjct' Narayana Murty N
2026-05-12 7:11 ` [PATCH 4/6] ppc/spapr: Advertise RTAS error injection call support via FDT property Narayana Murty N
2026-05-12 7:11 ` [PATCH 5/6] hw/ppc: Rename spapr_pci_vfio.c to spapr_pci_vfio_eeh.c Narayana Murty N
2026-05-12 7:54 ` Cédric Le Goater
2026-05-13 8:24 ` Narayana Murty N
2026-05-13 16:16 ` Pierrick Bouvier
2026-05-12 7:11 ` [PATCH 6/6] MAINTAINERS: Add entry for sPAPR PCI VFIO EEH support Narayana Murty N
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