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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: mcRsunVR/ZUX+G9BGxYsXttrw3x07LSiROaI2g/1ywiXVD5K4fdnopcHTxbqpN1L1GZ9Edi7/j4szob3Xt+NqNlydj02zMom7ecsXnJdt3NI70xMM+YDPTi4jNvabFi5mI2vBM3hhv3X2EjLCTL0JqmocM9aoj7G+eCnaWtYEf+PmpYJsGDl2k7V4r2gmleLaDWGWr7T4iZ6AKREcCJ3DeCw8uJhwZZsl68GsLvWSdd9NZeKey+p1N1E7wp3pxZ2wGnMti5KpjTcp+Z1GtTbSF2FGppIgxkzyrDalL2NzzHRfz5LoIbKTpp0DhhLHKptQT3CkvHrCusKRBwNxQeChBPrilvn+796eRs79PnfZRGOOKenDMkRyzdRJsN2Si2VdHbEPoZwUHhzoIMDrCV2IDCmw8fBDht9S8GSJtIw2TJgjGE2bJGkstPNMUK22QEs X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2026 15:52:50.9619 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e330fd87-eb49-4ca0-712b-08deb03e85a8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E64.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB9529 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" This adds a few, relatively minor, changes for FRL to clk_mgr, DSC, and HDCP blocks. Signed-off-by: Harry Wentland Reviewed-by: Fangzhi Zuo --- .../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 3 +++ .../display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c | 3 +++ .../display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 3 +++ .../display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c | 3 +++ .../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 12 ++++++++++++ .../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 14 ++++++++++++++ .../display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c | 18 ++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dsc/dsc.h | 5 +++++ drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c | 1 + 9 files changed, 62 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c index dc7f50095a13..00c4be7c3aa4 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c @@ -93,6 +93,9 @@ static int dcn31_get_active_display_cnt_wa( if (dc_is_dp_signal(stream->signal) && !stream->dpms_off) display_count++; + /* FRL can't be tracked by DIG enablement */ + if (dc_is_hdmi_frl_signal(stream->signal)) + display_count++; } for (i = 0; i < dc->link_count; i++) { diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c index 5fe59adc862f..dd6f11ecb9c9 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c @@ -127,6 +127,9 @@ static int dcn314_get_active_display_cnt_wa( if (dc_is_dp_signal(stream->signal) && !stream->dpms_off) display_count++; + /* FRL can't be tracked by DIG enablement */ + if (dc_is_hdmi_frl_signal(stream->signal)) + display_count++; } for (i = 0; i < dc->link_count; i++) { diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c index b6f26475ac16..75d39cb26dba 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c @@ -69,6 +69,9 @@ static int dcn315_get_active_display_cnt_wa( stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK || stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) tmds_present = true; + /* FRL can't be tracked by DIG enablement */ + if (dc_is_hdmi_frl_signal(stream->signal)) + display_count++; } for (i = 0; i < dc->link_count; i++) { diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c index 72a38f7a761c..c7fecbdfda2c 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c @@ -81,6 +81,9 @@ static int dcn316_get_active_display_cnt_wa( stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK || stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) tmds_present = true; + /* FRL can't be tracked by DIG enablement */ + if (dc_is_hdmi_frl_signal(stream->signal)) + display_count++; } for (i = 0; i < dc->link_count; i++) { diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index 2dc244d5a55f..be0e3836a6c1 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -283,6 +283,18 @@ static void dcn32_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, dto_params.otg_inst = pipe_ctx->stream_res.tg->inst; dto_params.ref_dtbclk_khz = ref_dtbclk_khz; + if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal) || + dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { + dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10; + + if (pipe_ctx->stream_res.audio != NULL) + dto_params.req_audio_dtbclk_khz = 24000; + } + + if (dc_is_hdmi_signal(pipe_ctx->stream->signal) || + dc_is_dvi_signal(pipe_ctx->stream->signal)) + dto_params.is_hdmi = true; + dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params); //dccg->funcs->set_audio_dtbclk_dto(clk_mgr->dccg, &dto_params); } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c index 6c6848e375e1..103013e2a0de 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c @@ -232,6 +232,8 @@ void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context if (old_pipe->stream && new_pipe->stream && old_pipe->stream == new_pipe->stream) { has_active_hpo = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(old_pipe) && dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(new_pipe); + has_active_hpo = has_active_hpo || (old_pipe->stream->signal == SIGNAL_TYPE_HDMI_FRL && + new_pipe->stream->signal == SIGNAL_TYPE_HDMI_FRL); } @@ -271,6 +273,18 @@ static void dcn35_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, dto_params.otg_inst = pipe_ctx->stream_res.tg->inst; dto_params.ref_dtbclk_khz = ref_dtbclk_khz; + if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal) || + dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { + dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10; + + if (pipe_ctx->stream_res.audio != NULL) + dto_params.req_audio_dtbclk_khz = 24000; + } + + if (dc_is_hdmi_signal(pipe_ctx->stream->signal) || + dc_is_dvi_signal(pipe_ctx->stream->signal)) + dto_params.is_hdmi = true; + dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params); //dccg->funcs->set_audio_dtbclk_dto(clk_mgr->dccg, &dto_params); } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c index 7c2b716d5d2a..5f9398745a38 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c @@ -542,6 +542,7 @@ static void dcn401_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr ASSERT(otg_master->stream_res.pix_clk_params.controller_id >= CONTROLLER_ID_D0); use_hpo_encoder = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(otg_master); + use_hpo_encoder |= dc_is_hdmi_frl_signal(otg_master->stream->signal); if (!use_hpo_encoder) continue; @@ -1095,6 +1096,9 @@ static unsigned int dcn401_build_update_display_clocks_sequence( bool update_dispclk = false; bool update_dppclk = false; bool dppclk_lowered = false; + struct pipe_ctx *otg_master; + bool frl_present = false; + unsigned int i; unsigned int num_steps = 0; @@ -1127,6 +1131,20 @@ static unsigned int dcn401_build_update_display_clocks_sequence( /* DCCG requires KHz precision for DTBCLK */ block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_DTBCLK; block_sequence[num_steps].params.update_hardmin_params.freq_mhz = (uint16_t)khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz); + for (i = 0; i < context->stream_count; i++) { + otg_master = resource_get_otg_master_for_stream( + &context->res_ctx, context->streams[i]); + if (otg_master != NULL && + otg_master->stream != NULL && + dc_is_hdmi_frl_signal(otg_master->stream->signal)) { + frl_present = true; + break; + } + } + if (frl_present) + block_sequence[num_steps].params.update_hardmin_params.freq_mhz = + (uint16_t)clk_mgr_base->bw_params->clk_table.entries[ + clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels - 1].dtbclk_mhz; block_sequence[num_steps].params.update_hardmin_params.response = &clk_mgr_base->clks.ref_dtbclk_khz; block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK; num_steps++; diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dsc.h index a16c60d8532f..ab37a7eaaf01 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dsc/dsc.h @@ -102,6 +102,11 @@ struct dsc_enc_caps { int32_t max_total_throughput_mps; /* Maximum total throughput with all the slices combined */ int32_t max_slice_width; uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */ + bool is_frl; + bool is_vic_all_bpp; + uint32_t total_chunk_kbytes; + uint32_t num_lanes; + uint32_t frl_rate; uint32_t edp_sink_max_bits_per_pixel; bool is_dp; }; diff --git a/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c b/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c index 73a1e6a03719..34fc9f56dbef 100644 --- a/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c +++ b/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c @@ -365,6 +365,7 @@ static const struct protection_properties *get_protection_properties_by_signal( case SIGNAL_TYPE_DVI_SINGLE_LINK: case SIGNAL_TYPE_DVI_DUAL_LINK: case SIGNAL_TYPE_HDMI_TYPE_A: + case SIGNAL_TYPE_HDMI_FRL: return &hdmi_14_protection; //todo version2.2 case SIGNAL_TYPE_DISPLAY_PORT: case SIGNAL_TYPE_DISPLAY_PORT_MST: -- 2.54.0