From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2239368D53 for ; Wed, 13 May 2026 04:06:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778645183; cv=none; b=Q9vBPt7h/mtL8aPOpGvQESpG40aqCXRupqUzzDAuzndXbS1/nrR8xDLMl1OAYUKEYRY1DddwEBW3jVgIri/azI1q4OBc2h5y+Mix+/JiSkZ1IZegbAXKUK/bfgcmqLxpIZEStJS+2UOdHGQ98XN5vl5qI5tdmWxByZRiG/x1cvQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778645183; c=relaxed/simple; bh=jpjHejlEtkGaBBk6MQW7sF5O/PptqQW8kQL4hQs6NV0=; h=From:Subject:To:Cc:In-Reply-To:References:Content-Type:Date: Message-Id; b=bX/abk+o/9D04qgJz+8zjlaVeCMA2E/mWCnTlAGPTfe4PySRjKWvjrZRq22IZDtqGZid5b3NWbgAbYAHoEAWlvlvMHwOalk1AqcsOldA0pzOjL7SijNPnwuCOcHBBatOREv6oTjbG5QR2ftaHigCpE0tGJsDfGLhiTIMymFkeJw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Q/h0K9NH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Q/h0K9NH" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 03F36C2BCC7; Wed, 13 May 2026 04:06:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778645183; bh=jpjHejlEtkGaBBk6MQW7sF5O/PptqQW8kQL4hQs6NV0=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date:From; b=Q/h0K9NHXyfsLN7uVdBYzGI3O9e3+P//r1i1TsNVyHEBRZ6eZInJa0MZ/0fBnGuZz fgPzf26JICX+19PIaGPUqqegV037UDKZFdz8Xf6093dwgv+9b2AJaBK3g7QdRiG8bj qHx7idQxBZk3JDq4mdVDfoxa4xhHqV2ZDUnhDlD8T6rb59bmULW42Xrdg5xuQlT5u/ 9Vlopud+4GX8V5AZKwtoefjLmfEOXhGLn5fLcgGyH+R3ImfslVwOfIL0sMVLLhgE7v I0Alrx7gN+KuHDyNBav+Svsm1TRSaKb00LCgscLW8XKtiXq7CuyPGG1HFM7myzA6Bc blTh2iCj5VAnw== From: sashiko-bot@kernel.org Subject: Re: [PATCH 2/4] arm64: dts: qcom: Introduce Shikra SoC base dtsi Reply-To: sashiko-reviews@lists.linux.dev To: "Komal Bajaj" Cc: linux-phy@lists.infradead.org, krzk+dt@kernel.org, devicetree@vger.kernel.org, neil.armstrong@linaro.org, olteanv@gmail.com, conor+dt@kernel.org, robh@kernel.org, vkoul@kernel.org In-Reply-To: <20260512-shikra-dt-v1-2-716438330dd0@oss.qualcomm.com> References: <20260512-shikra-dt-v1-2-716438330dd0@oss.qualcomm.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Date: Wed, 13 May 2026 04:06:22 +0000 Message-Id: <20260513040623.03F36C2BCC7@smtp.kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Thank you for your contribution! Sashiko AI review found 4 potential issue(= s) to consider: - [High] Invalid PPI interrupt numbers (1, 2, 3, 0) are specified for the A= RMv8 generic timer instead of the architecturally required numbers (13, 14,= 11, 10). - [Medium] The `sdhc_1` node incorrectly uses RPMh interconnect tags (`QCOM= _ICC_TAG_ALWAYS`, `QCOM_ICC_TAG_ACTIVE_ONLY`) on an RPM-based interconnect = topology. - [Medium] The USB SuperSpeed wakeup interrupt (`ss_phy_irq`) directly refe= rences the GIC instead of routing through the MPM, breaking system wake-up = from deep sleep. - [Low] The `sdhc_1` node uses the undeclared macro `RPMHPD_CX` for its `po= wer-domains` property, which will cause a Device Tree compiler syntax error. -- commit e2ee94ef3a5741f2cb9aae14dbef52c5f4a760f1 Author: Komal Bajaj Subject: arm64: dts: qcom: Introduce Shikra SoC base dtsi This commit adds initial device tree support for the Qualcomm Shikra SoC, an IoT-focused platform featuring a Cortex-A55 and Cortex-A78C cluster. It configures RPM-based power and clock management alongside various periphera= ls like USB, eMMC, and the generic timer. > diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/q= com/shikra.dtsi > new file mode 100644 > index 0000000000000..262c488add1ec > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi [ ... ] > + sdhc_1: mmc@4744000 { > + compatible =3D "qcom,shikra-sdhci", "qcom,sdhci-msm-v5"; > + > + reg =3D <0x0 0x04744000 0x0 0x1000>, > + <0x0 0x04745000 0x0 0x1000>; [ ... ] > + interconnects =3D <&system_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, > + <&mem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY > + &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ACTIVE_ONLY>; Since the Shikra SoC utilizes an RPM-based architecture, should this node u= se interconnect tags from qcom,rpm-icc.h (such as RPM_ALWAYS_TAG) instead?=20 Passing RPMh interconnect tags from qcom,icc.h to an RPM interconnect provi= der might result in unhandled parameters or silent bandwidth request failures. > + interconnect-names =3D "sdhc-ddr", > + "cpu-sdhc"; > + > + power-domains =3D <&rpmpd RPMHPD_CX>; Does this power-domains assignment use an undeclared macro? RPMHPD_CX belon= gs to RPMh-based power domains, while this platform relies on RPMPD. This looks like it will cause a dtc syntax error during the build. [ ... ] > + usb_1: usb@4e00000 { > + compatible =3D "qcom,shikra-dwc3", "qcom,snps-dwc3"; > + reg =3D <0x0 0x04e00000 0x0 0xfc100>; [ ... ] > + interrupts-extended =3D <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names =3D "dwc_usb3", > + "pwr_event", > + "qusb2_phy", > + "hs_phy_irq", > + "ss_phy_irq"; The mpm node correctly maps pin 12 to GIC SPI 422 for the DWC3 ss_phy_irq. Could routing this directly to the GIC here instead of hierarchically throu= gh the mpm (e.g., <&mpm 12 IRQ_TYPE_LEVEL_HIGH>) prevent the hardware from waking up from low-power states upon USB activity? [ ... ] > + timer { > + compatible =3D "arm,armv8-timer"; > + > + interrupts =3D , > + , > + , > + ; > + }; Are these PPI interrupt numbers correct for the ARMv8 generic timer? The architecturally defined numbers are typically 13 for Secure, 14 for Non-sec= ure, 11 for Virtual, and 10 for Hypervisor. Using invalid hardware IRQ lines here could prevent the kernel from receiving scheduler ticks and stall the boot. > +}; --=20 Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20260512-shikra-dt-= v1-0-716438330dd0@oss.qualcomm.com?part=3D2 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AFD7DCD37B6 for ; Wed, 13 May 2026 04:06:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Reply-To:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date: References:In-Reply-To:Cc:To:Subject:From:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=c7vj7gldPK2QK94pPRME5TOy5XACwidIMnTDDz5+tkE=; b=XsyL2fzWF+lxfY XQk06s4pK6XldOm8z/6KS/W1p7+9aVDNmxEuPXXrf0Ue7pnClkYotVdNrkLP5xq7rPKlf0N+szbW0 0TpeJxXn+pZOPZBGMp6xfY19y8agf5WrC2XT88ecDxHEaxYR0LnJPccTyHep2uq7c+clSld8rUTEl aiHyIu4mDhqzSDSR0GQCwyvYLPOdMLkC1ZYR5eTgbW9VaYI79tHtxacpfPlS3RY6gR/ADFrFjTFA8 ObosS7M/z5bPX1lrTh1ONWfOjhWRvOhFnqy5MFaa11Tb2+vpSr5z4qWcDMHunfEjUn+dVX/avsnee UGRIe0kaL2cX/ItWKcog==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wN0rc-00000001AML-10H8; Wed, 13 May 2026 04:06:28 +0000 Received: from tor.source.kernel.org ([2600:3c04:e001:324:0:1991:8:25]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wN0rZ-00000001AM2-3zKC for linux-phy@lists.infradead.org; Wed, 13 May 2026 04:06:26 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id A6B63600CB; Wed, 13 May 2026 04:06:23 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 03F36C2BCC7; Wed, 13 May 2026 04:06:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778645183; bh=jpjHejlEtkGaBBk6MQW7sF5O/PptqQW8kQL4hQs6NV0=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date:From; b=Q/h0K9NHXyfsLN7uVdBYzGI3O9e3+P//r1i1TsNVyHEBRZ6eZInJa0MZ/0fBnGuZz fgPzf26JICX+19PIaGPUqqegV037UDKZFdz8Xf6093dwgv+9b2AJaBK3g7QdRiG8bj qHx7idQxBZk3JDq4mdVDfoxa4xhHqV2ZDUnhDlD8T6rb59bmULW42Xrdg5xuQlT5u/ 9Vlopud+4GX8V5AZKwtoefjLmfEOXhGLn5fLcgGyH+R3ImfslVwOfIL0sMVLLhgE7v I0Alrx7gN+KuHDyNBav+Svsm1TRSaKb00LCgscLW8XKtiXq7CuyPGG1HFM7myzA6Bc blTh2iCj5VAnw== From: sashiko-bot@kernel.org Subject: Re: [PATCH 2/4] arm64: dts: qcom: Introduce Shikra SoC base dtsi To: "Komal Bajaj" Cc: linux-phy@lists.infradead.org, krzk+dt@kernel.org, devicetree@vger.kernel.org, neil.armstrong@linaro.org, olteanv@gmail.com, conor+dt@kernel.org, robh@kernel.org, vkoul@kernel.org In-Reply-To: <20260512-shikra-dt-v1-2-716438330dd0@oss.qualcomm.com> References: <20260512-shikra-dt-v1-2-716438330dd0@oss.qualcomm.com> Date: Wed, 13 May 2026 04:06:22 +0000 Message-Id: <20260513040623.03F36C2BCC7@smtp.kernel.org> X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: sashiko-reviews@lists.linux.dev MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org VGhhbmsgeW91IGZvciB5b3VyIGNvbnRyaWJ1dGlvbiEgU2FzaGlrbyBBSSByZXZpZXcgZm91bmQg NCBwb3RlbnRpYWwgaXNzdWUocykgdG8gY29uc2lkZXI6Ci0gW0hpZ2hdIEludmFsaWQgUFBJIGlu dGVycnVwdCBudW1iZXJzICgxLCAyLCAzLCAwKSBhcmUgc3BlY2lmaWVkIGZvciB0aGUgQVJNdjgg Z2VuZXJpYyB0aW1lciBpbnN0ZWFkIG9mIHRoZSBhcmNoaXRlY3R1cmFsbHkgcmVxdWlyZWQgbnVt YmVycyAoMTMsIDE0LCAxMSwgMTApLgotIFtNZWRpdW1dIFRoZSBgc2RoY18xYCBub2RlIGluY29y cmVjdGx5IHVzZXMgUlBNaCBpbnRlcmNvbm5lY3QgdGFncyAoYFFDT01fSUNDX1RBR19BTFdBWVNg LCBgUUNPTV9JQ0NfVEFHX0FDVElWRV9PTkxZYCkgb24gYW4gUlBNLWJhc2VkIGludGVyY29ubmVj dCB0b3BvbG9neS4KLSBbTWVkaXVtXSBUaGUgVVNCIFN1cGVyU3BlZWQgd2FrZXVwIGludGVycnVw dCAoYHNzX3BoeV9pcnFgKSBkaXJlY3RseSByZWZlcmVuY2VzIHRoZSBHSUMgaW5zdGVhZCBvZiBy b3V0aW5nIHRocm91Z2ggdGhlIE1QTSwgYnJlYWtpbmcgc3lzdGVtIHdha2UtdXAgZnJvbSBkZWVw IHNsZWVwLgotIFtMb3ddIFRoZSBgc2RoY18xYCBub2RlIHVzZXMgdGhlIHVuZGVjbGFyZWQgbWFj cm8gYFJQTUhQRF9DWGAgZm9yIGl0cyBgcG93ZXItZG9tYWluc2AgcHJvcGVydHksIHdoaWNoIHdp bGwgY2F1c2UgYSBEZXZpY2UgVHJlZSBjb21waWxlciBzeW50YXggZXJyb3IuCi0tCgpjb21taXQg ZTJlZTk0ZWYzYTU3NDFmMmNiOWFhZTE0ZGJlZjUyYzVmNGE3NjBmMQpBdXRob3I6IEtvbWFsIEJh amFqIDxrb21hbC5iYWphakBvc3MucXVhbGNvbW0uY29tPgpTdWJqZWN0OiBhcm02NDogZHRzOiBx Y29tOiBJbnRyb2R1Y2UgU2hpa3JhIFNvQyBiYXNlIGR0c2kKClRoaXMgY29tbWl0IGFkZHMgaW5p dGlhbCBkZXZpY2UgdHJlZSBzdXBwb3J0IGZvciB0aGUgUXVhbGNvbW0gU2hpa3JhIFNvQywgYW4K SW9ULWZvY3VzZWQgcGxhdGZvcm0gZmVhdHVyaW5nIGEgQ29ydGV4LUE1NSBhbmQgQ29ydGV4LUE3 OEMgY2x1c3Rlci4gSXQKY29uZmlndXJlcyBSUE0tYmFzZWQgcG93ZXIgYW5kIGNsb2NrIG1hbmFn ZW1lbnQgYWxvbmdzaWRlIHZhcmlvdXMgcGVyaXBoZXJhbHMKbGlrZSBVU0IsIGVNTUMsIGFuZCB0 aGUgZ2VuZXJpYyB0aW1lci4KCj4gZGlmZiAtLWdpdCBhL2FyY2gvYXJtNjQvYm9vdC9kdHMvcWNv bS9zaGlrcmEuZHRzaSBiL2FyY2gvYXJtNjQvYm9vdC9kdHMvcWNvbS9zaGlrcmEuZHRzaQo+IG5l dyBmaWxlIG1vZGUgMTAwNjQ0Cj4gaW5kZXggMDAwMDAwMDAwMDAwMC4uMjYyYzQ4OGFkZDFlYwo+ IC0tLSAvZGV2L251bGwKPiArKysgYi9hcmNoL2FybTY0L2Jvb3QvZHRzL3Fjb20vc2hpa3JhLmR0 c2kKClsgLi4uIF0KCj4gKwkJc2RoY18xOiBtbWNANDc0NDAwMCB7Cj4gKwkJCWNvbXBhdGlibGUg PSAicWNvbSxzaGlrcmEtc2RoY2kiLCAicWNvbSxzZGhjaS1tc20tdjUiOwo+ICsKPiArCQkJcmVn ID0gPDB4MCAweDA0NzQ0MDAwIDB4MCAweDEwMDA+LAo+ICsJCQkgICAgICA8MHgwIDB4MDQ3NDUw MDAgMHgwIDB4MTAwMD47CgpbIC4uLiBdCgo+ICsJCQlpbnRlcmNvbm5lY3RzID0gPCZzeXN0ZW1f bm9jIE1BU1RFUl9TRENDXzEgUUNPTV9JQ0NfVEFHX0FMV0FZUwo+ICsJCQkJCSZtY192aXJ0IFNM QVZFX0VCSV9DSDAgUUNPTV9JQ0NfVEFHX0FMV0FZUz4sCj4gKwkJCQkJPCZtZW1fbm9jIE1BU1RF Ul9BTVBTU19NMCBRQ09NX0lDQ19UQUdfQUNUSVZFX09OTFkKPiArCQkJCQkmY29uZmlnX25vYyBT TEFWRV9TRENDXzEgUUNPTV9JQ0NfVEFHX0FDVElWRV9PTkxZPjsKClNpbmNlIHRoZSBTaGlrcmEg U29DIHV0aWxpemVzIGFuIFJQTS1iYXNlZCBhcmNoaXRlY3R1cmUsIHNob3VsZCB0aGlzIG5vZGUg dXNlCmludGVyY29ubmVjdCB0YWdzIGZyb20gcWNvbSxycG0taWNjLmggKHN1Y2ggYXMgUlBNX0FM V0FZU19UQUcpIGluc3RlYWQ/IApQYXNzaW5nIFJQTWggaW50ZXJjb25uZWN0IHRhZ3MgZnJvbSBx Y29tLGljYy5oIHRvIGFuIFJQTSBpbnRlcmNvbm5lY3QgcHJvdmlkZXIKbWlnaHQgcmVzdWx0IGlu IHVuaGFuZGxlZCBwYXJhbWV0ZXJzIG9yIHNpbGVudCBiYW5kd2lkdGggcmVxdWVzdCBmYWlsdXJl cy4KCj4gKwkJCWludGVyY29ubmVjdC1uYW1lcyA9ICJzZGhjLWRkciIsCj4gKwkJCQkJICAgICAi Y3B1LXNkaGMiOwo+ICsKPiArCQkJcG93ZXItZG9tYWlucyA9IDwmcnBtcGQgUlBNSFBEX0NYPjsK CkRvZXMgdGhpcyBwb3dlci1kb21haW5zIGFzc2lnbm1lbnQgdXNlIGFuIHVuZGVjbGFyZWQgbWFj cm8/IFJQTUhQRF9DWCBiZWxvbmdzCnRvIFJQTWgtYmFzZWQgcG93ZXIgZG9tYWlucywgd2hpbGUg dGhpcyBwbGF0Zm9ybSByZWxpZXMgb24gUlBNUEQuIFRoaXMgbG9va3MKbGlrZSBpdCB3aWxsIGNh dXNlIGEgZHRjIHN5bnRheCBlcnJvciBkdXJpbmcgdGhlIGJ1aWxkLgoKWyAuLi4gXQoKPiArCQl1 c2JfMTogdXNiQDRlMDAwMDAgewo+ICsJCQljb21wYXRpYmxlID0gInFjb20sc2hpa3JhLWR3YzMi LCAicWNvbSxzbnBzLWR3YzMiOwo+ICsJCQlyZWcgPSA8MHgwIDB4MDRlMDAwMDAgMHgwIDB4ZmMx MDA+OwoKWyAuLi4gXQoKPiArCQkJaW50ZXJydXB0cy1leHRlbmRlZCA9IDwmaW50YyBHSUNfU1BJ IDI1NSBJUlFfVFlQRV9MRVZFTF9ISUdIPiwKPiArCQkJCQkgICAgICA8JmludGMgR0lDX1NQSSAz MDIgSVJRX1RZUEVfTEVWRUxfSElHSD4sCj4gKwkJCQkJICAgICAgPCZpbnRjIEdJQ19TUEkgMjYw IElSUV9UWVBFX0xFVkVMX0hJR0g+LAo+ICsJCQkJCSAgICAgIDwmaW50YyBHSUNfU1BJIDI1NCBJ UlFfVFlQRV9MRVZFTF9ISUdIPiwKPiArCQkJCQkgICAgICA8JmludGMgR0lDX1NQSSA0MjIgSVJR X1RZUEVfTEVWRUxfSElHSD47Cj4gKwkJCWludGVycnVwdC1uYW1lcyA9ICJkd2NfdXNiMyIsCj4g KwkJCQkJICAicHdyX2V2ZW50IiwKPiArCQkJCQkgICJxdXNiMl9waHkiLAo+ICsJCQkJCSAgImhz X3BoeV9pcnEiLAo+ICsJCQkJCSAgInNzX3BoeV9pcnEiOwoKVGhlIG1wbSBub2RlIGNvcnJlY3Rs eSBtYXBzIHBpbiAxMiB0byBHSUMgU1BJIDQyMiBmb3IgdGhlIERXQzMgc3NfcGh5X2lycS4KQ291 bGQgcm91dGluZyB0aGlzIGRpcmVjdGx5IHRvIHRoZSBHSUMgaGVyZSBpbnN0ZWFkIG9mIGhpZXJh cmNoaWNhbGx5IHRocm91Z2gKdGhlIG1wbSAoZS5nLiwgPCZtcG0gMTIgSVJRX1RZUEVfTEVWRUxf SElHSD4pIHByZXZlbnQgdGhlIGhhcmR3YXJlIGZyb20Kd2FraW5nIHVwIGZyb20gbG93LXBvd2Vy IHN0YXRlcyB1cG9uIFVTQiBhY3Rpdml0eT8KClsgLi4uIF0KCj4gKwl0aW1lciB7Cj4gKwkJY29t cGF0aWJsZSA9ICJhcm0sYXJtdjgtdGltZXIiOwo+ICsKPiArCQlpbnRlcnJ1cHRzID0gPEdJQ19Q UEkgMSBJUlFfVFlQRV9MRVZFTF9MT1c+LAo+ICsJCQkgICAgIDxHSUNfUFBJIDIgSVJRX1RZUEVf TEVWRUxfTE9XPiwKPiArCQkJICAgICA8R0lDX1BQSSAzIElSUV9UWVBFX0xFVkVMX0xPVz4sCj4g KwkJCSAgICAgPEdJQ19QUEkgMCBJUlFfVFlQRV9MRVZFTF9MT1c+Owo+ICsJfTsKCkFyZSB0aGVz ZSBQUEkgaW50ZXJydXB0IG51bWJlcnMgY29ycmVjdCBmb3IgdGhlIEFSTXY4IGdlbmVyaWMgdGlt ZXI/IFRoZQphcmNoaXRlY3R1cmFsbHkgZGVmaW5lZCBudW1iZXJzIGFyZSB0eXBpY2FsbHkgMTMg Zm9yIFNlY3VyZSwgMTQgZm9yIE5vbi1zZWN1cmUsCjExIGZvciBWaXJ0dWFsLCBhbmQgMTAgZm9y IEh5cGVydmlzb3IuIFVzaW5nIGludmFsaWQgaGFyZHdhcmUgSVJRIGxpbmVzIGhlcmUKY291bGQg cHJldmVudCB0aGUga2VybmVsIGZyb20gcmVjZWl2aW5nIHNjaGVkdWxlciB0aWNrcyBhbmQgc3Rh bGwgdGhlIGJvb3QuCgo+ICt9OwoKLS0gClNhc2hpa28gQUkgcmV2aWV3IMK3IGh0dHBzOi8vc2Fz aGlrby5kZXYvIy9wYXRjaHNldC8yMDI2MDUxMi1zaGlrcmEtZHQtdjEtMC03MTY0MzgzMzBkZDBA b3NzLnF1YWxjb21tLmNvbT9wYXJ0PTIKCi0tIApsaW51eC1waHkgbWFpbGluZyBsaXN0CmxpbnV4 LXBoeUBsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHBzOi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWls bWFuL2xpc3RpbmZvL2xpbnV4LXBoeQo=