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Wed, 13 May 2026 09:19:14 +0200 From: Wadim Egorov To: , , , , CC: , Subject: [PATCH 7/7] doc: board: phytec: Document DDR size override Kconfigs Date: Wed, 13 May 2026 09:19:05 +0200 Message-ID: <20260513071905.83522-8-w.egorov@phytec.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260513071905.83522-1-w.egorov@phytec.de> References: <20260513071905.83522-1-w.egorov@phytec.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.25.0.51] X-ClientProxiedBy: Postix.phytec.de (172.25.0.11) To Postix.phytec.de (172.25.0.11) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AMS0EPF0000019B:EE_|PAXP195MB1168:EE_ X-MS-Office365-Filtering-Correlation-Id: 836101fa-a06f-402a-9214-08deb0bff195 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700016|1800799024|82310400026|376014|11063799003|22082099003|18002099003|56012099003; X-Microsoft-Antispam-Message-Info: dpqRZ7lircSTGkkygHQjjiBSIk/oVU26w1MTRrZKqAIUPZdZdVwU6p4AHZirbh69aKW1g2dLaqE1BGxVZGYqkXjkEi4382TZWNTjQpzyooMMHneBs52kJTi/pQWFqpXo9BMeVOPzy/07VoYRh35ZfxA6Mce79PlFtPyaP51c4dUCzmh3hVpGt2smQJ50E1BU/XSdYOn57NrYlZmB8oKL53Ua856XrfcwKhrQYNCmcMWNLSi4Hj6w14XIdrtGuX+6kqxM20vJlS6fTM5ouz8NF3de+Dnn33uAmA/jrdopgj7fnxiD6AwMnl4eL2hmIdjfi4XoPJzlc9cwahRyxu9G2g1aO+D9iAptBSYQfHZkaRUqZhk87nW8erJvWs/i3jm4mMbaTJhlIw8AGVoxspO5mBy8qIkQypZyxP1015nOfrXQHkZiQhoJXnyo88lGXv1YJ1JtdpA5dcC1WGc1t5iNrAnvVxgoOwN6RMxcuSK+lBbnxuV0UhFv10aWMdu9arvFlcBq29ih+15u2uM+/ZpjVIKBXtcIWk8Jh7LPUz/Fo32pLnk65NWU2AzyKHtT2GUoRHbrD6KZxfrpPM4bxJJ0C7/UfCKUmfGREzH5Ws2Frfz+OMwZnVVyyeFe7onVOaDDqvbzwcDUMitHhixK3p7kpP0x0XhC3MQ1SSfd/fsl6QNFdc9CQN1uFCfUH8Ln7TUG2b2UvtoVQ3+MA4/gceGbdDHoFvX6XglMXVyOjq27rlw= X-Forefront-Antispam-Report: CIP:91.26.50.189; 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Ip=[91.26.50.189]; Helo=[Postix.phytec.de] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF0000019B.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXP195MB1168 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The phyCORE-AM62x and phyCORE-AM64x R5 SPL detects the populated DDR size from the SoM EEPROM and falls back to 2 GB if detection fails. For boards without a populated EEPROM or if no detection needed, the detection can be bypassed via CONFIG_PHYCORE_AM6{2,4}X_RAM_SIZE_FIX and one of the CONFIG_PHYCORE_AM6{2,4}X_RAM_SIZE_ choices. Add a "DDR RAM Size" section to both board docs describing this behaviour and listing the available size options (1/2/4 GB for AM62x, 1/2 GB for AM64x). Signed-off-by: Wadim Egorov --- doc/board/phytec/phycore-am62x.rst | 19 +++++++++++++++++++ doc/board/phytec/phycore-am64x.rst | 18 ++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/doc/board/phytec/phycore-am62x.rst b/doc/board/phytec/phycore-am62x.rst index f5a0d51240a..5349ba429d4 100644 --- a/doc/board/phytec/phycore-am62x.rst +++ b/doc/board/phytec/phycore-am62x.rst @@ -177,6 +177,25 @@ Boot switches should be changed with power off. - 11001010 - 00100000 +DDR RAM Size +------------ + +By default, the R5 SPL detects the populated DDR size by reading the SoM +EEPROM and configures the DDR controller and the U-Boot device-tree memory +node accordingly. The phyCORE-AM62x is available with 1 GB, 2 GB, or 4 GB of +DDR. If the EEPROM cannot be read or is invalid, the SPL falls back to a +2 GB configuration. + +EEPROM-based detection can be bypassed by enabling +`CONFIG_PHYCORE_AM62X_RAM_SIZE_FIX` in the R5 defconfig and selecting one of: + +* `CONFIG_PHYCORE_AM62X_RAM_SIZE_1GB` +* `CONFIG_PHYCORE_AM62X_RAM_SIZE_2GB` +* `CONFIG_PHYCORE_AM62X_RAM_SIZE_4GB` + +This is mainly useful if no detection is needed or for boards without a +populated SoM EEPROM. + .. include:: k3-common.rst Further Information diff --git a/doc/board/phytec/phycore-am64x.rst b/doc/board/phytec/phycore-am64x.rst index c6677f6a440..20887d443a9 100644 --- a/doc/board/phytec/phycore-am64x.rst +++ b/doc/board/phytec/phycore-am64x.rst @@ -175,6 +175,24 @@ Boot switches should be changed with power off. - 11011100 - 00000000 +DDR RAM Size +------------ + +By default, the R5 SPL detects the populated DDR size by reading the SoM +EEPROM and configures the DDR controller and the U-Boot device-tree memory +node accordingly. The phyCORE-AM64x is available with 1 GB or 2 GB of DDR. +If the EEPROM cannot be read or is invalid, the SPL falls back to a 2 GB +configuration. + +EEPROM-based detection can be bypassed by enabling +`CONFIG_PHYCORE_AM64X_RAM_SIZE_FIX` in the R5 defconfig and selecting one of: + +* `CONFIG_PHYCORE_AM64X_RAM_SIZE_1GB` +* `CONFIG_PHYCORE_AM64X_RAM_SIZE_2GB` + +This is mainly useful if no detection is needed or for boards without a +populated SoM EEPROM. + .. include:: k3-common.rst Further Information -- 2.48.1