From: Boris Brezillon <boris.brezillon@collabora.com>
To: Steven Price <steven.price@arm.com>
Cc: Liviu Dudau <liviu.dudau@arm.com>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 08/10] drm/panthor: Automatically enable interrupts in panthor_fw_wait_acks()
Date: Wed, 13 May 2026 17:42:22 +0200 [thread overview]
Message-ID: <20260513174222.70b6d2a2@fedora> (raw)
In-Reply-To: <3c721f22-d1a7-474e-8276-f0afc7cd9a0b@arm.com>
On Wed, 13 May 2026 16:02:11 +0100
Steven Price <steven.price@arm.com> wrote:
> >>>> It seems to work, although I'm lightly uneasy about this because I'm not
> >>>> entirely sure whether the FW will immediately see the updates to
> >>>> ack_irq_mask and therefore whether there's a possibility to miss an
> >>>> event and be stuck waiting for the timeout.
> >>>>
> >>>> Memory models are not my strong point, OpenAI tells me the sequence
> >>>> should be something like:
> >>>>
> >>>> scoped_guard(spinlock_irqsave, lock) {
> >>>> u32 ack_irq_mask = READ_ONCE(*ack_irq_mask_ptr);
> >>>>
> >>>> WRITE_ONCE(*ack_irq_mask_ptr, ack_irq_mask | req_mask);
> >>>> }
> >>>
> >>> Is this really needed? In which situation would the compiler/CPU decide
> >>> to re-order this read_update_modify sequence?
> >>
> >> I think that's the AI being a bit overzealous, but in general WRITE_ONCE
> >> is necessary to avoid some surprising effects. In theory the compiler
> >> can decide to perform multiple writes if it's non-volatile. I.e. a
> >> sequence like:
> >>
> >> u32 old_mask = *ack_irq_mask_ptr;
> >> if (condition)
> >> *ack_irq_mask_ptr = 0;
> >> else
> >> *ack_irq_mask_ptr |= req_mask;
> >>
> >> Can be 'optimised' to:
> >>
> >> u32 old_mask = *ack_irq_mask_ptr;
> >> *ack_irq_mask_ptr = 0;
> >> if (!condition)
> >> *ack_irq_mask_ptr = old_mask | req_mask;
> >>
> >> In which the compiler has changed the (!condition) path to do two writes
> >> one of which "should never be seen".
> >>
> >> Given that the compiler shouldn't be able to move any of the effects
> >> outside of the scoped_guard(), and since there's only one operation then
> >> I can't see how a compiler would screw it up - but the compiler is
> >> technically free to do so.
> >
> > Sure, I'm not saying read_modify_write is atomic per-se (even though
> > I'd be surprised if the compiler wasn't generating instructions that
> > are atomic in the end), but it is thread-safe because of the spinlock
> > covering the read_modify_write op.
>
> But one of the "threads" is the MCU which isn't using the spinlock -
> which is why it's a problem if the compiler left the value in a 'random'
> state even if it's all fixed up by the time the spinlock is released.
Okay, I see what you mean. I truly hope it's not random values, but if
it goes
X -> 0 -> X | Y
or
X -> 0 -> X & ~Y
that's already problematic, because we'd lose events.
>
> Like you say I would be very surprised if a compiler messed it up in
> this case.
I'll add the READ/WRITE_ONCE() and add a comment to make sure we don't
forget why they are needed (in theory).
next prev parent reply other threads:[~2026-05-13 15:42 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-29 9:38 [PATCH 00/10] drm/panthor: Reduce dma_fence signalling latency Boris Brezillon
2026-04-29 9:38 ` [PATCH 01/10] drm/panthor: Make panthor_irq::state a non-atomic field Boris Brezillon
2026-04-29 12:29 ` Liviu Dudau
2026-05-01 13:17 ` Steven Price
2026-04-29 9:38 ` [PATCH 02/10] drm/panthor: Move the register accessors before the IRQ helpers Boris Brezillon
2026-04-29 12:31 ` Liviu Dudau
2026-05-01 13:17 ` Steven Price
2026-04-29 9:38 ` [PATCH 03/10] drm/panthor: Replace the panthor_irq macro machinery by inline helpers Boris Brezillon
2026-04-30 9:40 ` Karunika Choo
2026-04-30 10:38 ` Boris Brezillon
2026-05-01 13:22 ` Steven Price
2026-04-29 9:38 ` [PATCH 04/10] drm/panthor: Extend the IRQ logic to allow fast/raw IRQ handlers Boris Brezillon
2026-04-29 13:32 ` Liviu Dudau
2026-05-01 13:28 ` Steven Price
2026-04-29 9:38 ` [PATCH 05/10] drm/panthor: Make panthor_fw_{update,toggle}_reqs() callable from IRQ context Boris Brezillon
2026-04-29 13:33 ` Liviu Dudau
2026-05-01 13:39 ` [PATCH 05/10] drm/panthor: Make panthor_fw_{update, toggle}_reqs() " Steven Price
2026-04-29 9:38 ` [PATCH 06/10] drm/panthor: Prepare the scheduler logic for FW events in " Boris Brezillon
2026-05-01 13:47 ` Steven Price
2026-05-04 9:34 ` Boris Brezillon
2026-04-29 9:38 ` [PATCH 07/10] drm/panthor: Automate CSG IRQ processing at group unbind time Boris Brezillon
2026-05-01 13:53 ` Steven Price
2026-05-04 15:00 ` Boris Brezillon
2026-04-29 9:38 ` [PATCH 08/10] drm/panthor: Automatically enable interrupts in panthor_fw_wait_acks() Boris Brezillon
2026-05-01 14:20 ` Steven Price
2026-05-04 11:02 ` Boris Brezillon
2026-05-06 14:35 ` Steven Price
2026-05-06 16:08 ` Boris Brezillon
2026-05-13 15:02 ` Steven Price
2026-05-13 15:42 ` Boris Brezillon [this message]
2026-04-29 9:38 ` [PATCH 09/10] drm/panthor: Process FW events in IRQ context Boris Brezillon
2026-05-01 14:38 ` Steven Price
2026-04-29 9:38 ` [PATCH 10/10] drm/panthor: Introduce interrupt coalescing support for job IRQs Boris Brezillon
2026-05-01 14:57 ` Steven Price
2026-05-04 11:15 ` Boris Brezillon
2026-04-29 9:59 ` [PATCH 00/10] drm/panthor: Reduce dma_fence signalling latency Boris Brezillon
2026-04-29 10:36 ` Boris Brezillon
2026-05-05 8:54 ` Boris Brezillon
2026-05-05 16:12 ` Liviu Dudau
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