Re: [PATCH] MAINTAINERS: Mark Microchip PolarFire SoC as Odd Fixes

[Conor Dooley <conor@kernel.org>]

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On Thu, May 14, 2026 at 09:54:43AM +1000, Alistair Francis wrote:
> On Thu, May 14, 2026 at 7:26 AM Conor Dooley <conor@kernel.org> wrote:
> >
> > On Wed, May 13, 2026 at 08:10:06AM +0200, Philippe Mathieu-Daudé wrote:
> > > On 13/5/26 04:38, alistair23@gmail.com wrote:
> > > > From: Alistair Francis <alistair.francis@wdc.com>
> > > >
> > > > Mark the "Microchip PolarFire SoC Icicle Kit" as Odd Fixes and enlist
> > > > Conor and Sebastian as people to help deal with the fixes.
> > > >
> > > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > > > ---
> > > > Conor let me know if it should be a different address
> > > >
> > > >   MAINTAINERS | 4 +++-
> > > >   1 file changed, 3 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/MAINTAINERS b/MAINTAINERS
> > > > index 952ed683bb..9626eb1ea9 100644
> > > > --- a/MAINTAINERS
> > > > +++ b/MAINTAINERS
> > > > @@ -1751,8 +1751,10 @@ F: target/riscv/xlrbr.decode
> > > >   F: tests/tcg/riscv64/test-crc32.S
> > > >   Microchip PolarFire SoC Icicle Kit
> > > > +M: Conor Dooley <conor@kernel.org>
> > > > +M: Sebastian Huber <sebastian.huber@embedded-brains.de>
> > >
> > > Maybe worth having a look at Guenter's following patch for this
> > > machine:
> > > https://github.com/groeck/qemu/commit/1a66d5b4e5fe9
> >
> > Ye, I can do that. It looks mostly pretty sane, but needs a bit of
> > cleanup I think before it is really applicable.
> >
> > Does it matter if the rates the PLLs report are accurate btw? Since
> 
> You know the hardware better than us. Generally if it allows the guest
> boot and the values are sane then that's probably fine

In that case, there's very little that needs doing with it IMO.
Dropping this one line here is probably sufficient:
https://github.com/groeck/qemu/commit/1a66d5b4e5fe9#diff-9d9266aa5117a927eda2de5ec50e77c41664adfbf48599ffaa58c9e7def28d0dR98-R116

I'll test that out and see.

> 
> Alistair
> 
> > everything here is emulated, it shouldn't matter if the PLLs run say all
> > at 100 MHz instead of one at 100 and one at 40, right? They're just used
> > to clock things like i2c or pwm controllers.
> 

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