From: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com,
chao.liu.zevorn@gmail.com, leif.lindholm@oss.qualcomm.com,
andrew.jones@oss.qualcomm.com, Fei Wu <wu.fei9@sanechips.com.cn>,
Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Subject: [PATCH v6 2/4] target/riscv: Add server platform reference cpu
Date: Thu, 14 May 2026 17:46:38 -0300 [thread overview]
Message-ID: <20260514204640.2540054-3-daniel.barboza@oss.qualcomm.com> (raw)
In-Reply-To: <20260514204640.2540054-1-daniel.barboza@oss.qualcomm.com>
From: Fei Wu <wu.fei9@sanechips.com.cn>
The harts requirements of RISC-V server platform [1] require RVA23 ISA
profile support and others.
This patch provides a new "riscv-server-ref" CPU to go along with the
future "riscv-server-ref" board.
[1] https://github.com/riscv-non-isa/riscv-server-platform/blob/main/server_platform_requirements.adoc
Signed-off-by: Fei Wu <wu.fei9@sanechips.com.cn>
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 11 +++++++++++
2 files changed, 12 insertions(+)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 30dcdcfaae..a150acd151 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -42,6 +42,7 @@
#define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64")
#define TYPE_RISCV_CPU_RVA23U64 RISCV_CPU_TYPE_NAME("rva23u64")
#define TYPE_RISCV_CPU_RVA23S64 RISCV_CPU_TYPE_NAME("rva23s64")
+#define TYPE_RISCV_CPU_RVSERVER_REF RISCV_CPU_TYPE_NAME("riscv-server-ref")
#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
#define TYPE_RISCV_CPU_SIFIVE_E RISCV_CPU_TYPE_NAME("sifive-e")
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 586683b28a..c81aab08cd 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -3401,6 +3401,17 @@ static const TypeInfo riscv_cpu_type_infos[] = {
#endif
),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RVSERVER_REF, TYPE_RISCV_BARE_CPU,
+ .misa_mxl_max = MXL_RV64,
+ .profile = &RVA23S64,
+
+ .cfg.ext_zkr = true,
+ .cfg.ext_svadu = true,
+ .cfg.ext_sdext = true,
+
+ .cfg.max_satp_mode = VM_1_10_SV48,
+ ),
+
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU,
.cfg.max_satp_mode = VM_1_10_SV57,
--
2.43.0
next prev parent reply other threads:[~2026-05-14 20:48 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-14 20:46 [PATCH v6 0/4] hw/riscv: Server Platform Reference Board Daniel Henrique Barboza
2026-05-14 20:46 ` [PATCH v6 1/4] target/riscv/cpu.c: remove 'bare' condition for .profile Daniel Henrique Barboza
2026-05-15 3:13 ` Chao Liu
2026-05-14 20:46 ` Daniel Henrique Barboza [this message]
2026-05-15 3:14 ` [PATCH v6 2/4] target/riscv: Add server platform reference cpu Chao Liu
2026-05-14 20:46 ` [PATCH v6 3/4] hw/riscv: server platform reference machine Daniel Henrique Barboza
2026-05-15 3:14 ` Chao Liu
2026-05-14 20:46 ` [PATCH v6 4/4] docs: add riscv-server-ref.rst Daniel Henrique Barboza
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