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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-45da0a19a0csm15051893f8f.20.2026.05.15.07.11.47 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 15 May 2026 07:11:48 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Richard Henderson , qemu-arm@nongnu.org, Joel Stanley , Kane Chen , Troy Lee , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier , Jamin Lin , Steven Lee , Andrew Jeffery , Manos Pitsidianakis Subject: [PATCH v6 10/20] target/arm: Restrict IDAU interface to TCG namespace Date: Fri, 15 May 2026 16:10:21 +0200 Message-ID: <20260515141032.3271-11-philmd@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260515141032.3271-1-philmd@linaro.org> References: <20260515141032.3271-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Emphasis the IDAU interface is restricted to TCG by moving the header under target/arm/tcg/. Move the definition to cpu-v7m.c which also contains v7/v8 hardware (NVIC), keeping only CPU types in cpu32.c. Reviewed-by: Pierrick Bouvier Signed-off-by: Philippe Mathieu-Daudé --- include/hw/arm/armv7m.h | 2 +- include/hw/misc/tz-msc.h | 2 +- target/arm/{ => tcg}/idau.h | 4 ++-- hw/arm/armv7m.c | 2 +- target/arm/cpu.c | 2 +- target/arm/ptw.c | 2 +- target/arm/tcg/cpu-v7m.c | 11 +++++++++++ target/arm/tcg/cpu32.c | 8 -------- 8 files changed, 18 insertions(+), 15 deletions(-) rename target/arm/{ => tcg}/idau.h (97%) diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h index 98ad08db036..70555962bb9 100644 --- a/include/hw/arm/armv7m.h +++ b/include/hw/arm/armv7m.h @@ -13,7 +13,7 @@ #include "hw/core/sysbus.h" #include "hw/intc/armv7m_nvic.h" #include "hw/misc/armv7m_ras.h" -#include "target/arm/idau.h" +#include "target/arm/tcg/idau.h" #include "qom/object.h" #include "hw/core/clock.h" diff --git a/include/hw/misc/tz-msc.h b/include/hw/misc/tz-msc.h index 07112d8caa3..6cf4c6b09eb 100644 --- a/include/hw/misc/tz-msc.h +++ b/include/hw/misc/tz-msc.h @@ -51,7 +51,7 @@ #define TZ_MSC_H #include "hw/core/sysbus.h" -#include "target/arm/idau.h" +#include "target/arm/tcg/idau.h" #include "qom/object.h" #define TYPE_TZ_MSC "tz-msc" diff --git a/target/arm/idau.h b/target/arm/tcg/idau.h similarity index 97% rename from target/arm/idau.h rename to target/arm/tcg/idau.h index 0ef5251971d..e5736ad848d 100644 --- a/target/arm/idau.h +++ b/target/arm/tcg/idau.h @@ -25,8 +25,8 @@ * connected to the CPU using a link property. */ -#ifndef TARGET_ARM_IDAU_H -#define TARGET_ARM_IDAU_H +#ifndef TARGET_ARM_TCG_IDAU_H +#define TARGET_ARM_TCG_IDAU_H #include "qom/object.h" diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index a29eab6c915..68a1cbd6316 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -20,7 +20,7 @@ #include "qemu/error-report.h" #include "qemu/module.h" #include "qemu/log.h" -#include "target/arm/idau.h" +#include "target/arm/tcg/idau.h" #include "target/arm/cpu.h" #include "target/arm/cpu-features.h" #include "target/arm/cpu-qom.h" diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 31e0a12a986..76f5909e902 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -24,7 +24,6 @@ #include "qemu/log.h" #include "exec/page-vary.h" #include "system/whpx.h" -#include "target/arm/idau.h" #include "qemu/module.h" #include "qapi/error.h" #include "cpu.h" @@ -42,6 +41,7 @@ #include "hw/intc/arm_gicv5_stream.h" #ifdef CONFIG_TCG #include "hw/intc/armv7m_nvic.h" +#include "target/arm/tcg/idau.h" #endif /* CONFIG_TCG */ #endif /* !CONFIG_USER_ONLY */ #include "system/tcg.h" diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8706dd59dd6..a4842a4b62b 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -17,7 +17,7 @@ #include "cpu.h" #include "internals.h" #include "cpu-features.h" -#include "idau.h" +#include "target/arm/tcg/idau.h" typedef struct S1Translate { /* diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index dc249ce1f14..02abd831e6a 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -11,6 +11,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "accel/tcg/cpu-ops.h" +#include "target/arm/tcg/idau.h" #include "internals.h" #if !defined(CONFIG_USER_ONLY) @@ -40,6 +41,16 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) return ret; } +static const TypeInfo arm_v8m_types[] = { + { + .name = TYPE_IDAU_INTERFACE, + .parent = TYPE_INTERFACE, + .class_size = sizeof(IDAUInterfaceClass), + } +}; + +DEFINE_TYPES(arm_v8m_types) + #endif /* !CONFIG_USER_ONLY */ static void cortex_m0_initfn(Object *obj) diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 2127d456ad6..73d21c6cf7d 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -12,7 +12,6 @@ #include "cpu.h" #include "accel/tcg/cpu-ops.h" #include "internals.h" -#include "target/arm/idau.h" #if !defined(CONFIG_USER_ONLY) #include "hw/core/boards.h" #endif @@ -899,17 +898,10 @@ static const ARMCPUInfo arm_tcg_cpus[] = { #endif }; -static const TypeInfo idau_interface_type_info = { - .name = TYPE_IDAU_INTERFACE, - .parent = TYPE_INTERFACE, - .class_size = sizeof(IDAUInterfaceClass), -}; - static void arm_tcg_cpu_register_types(void) { size_t i; - type_register_static(&idau_interface_type_info); for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) { arm_cpu_register(&arm_tcg_cpus[i]); } -- 2.53.0