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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48fead1c364sm16411955e9.8.2026.05.15.07.11.55 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 15 May 2026 07:11:55 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Richard Henderson , qemu-arm@nongnu.org, Joel Stanley , Kane Chen , Troy Lee , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier , Jamin Lin , Steven Lee , Andrew Jeffery , Manos Pitsidianakis Subject: [PATCH v6 11/20] target/arm: Rename Aarch64-specific methods Date: Fri, 15 May 2026 16:10:22 +0200 Message-ID: <20260515141032.3271-12-philmd@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260515141032.3271-1-philmd@linaro.org> References: <20260515141032.3271-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- target/arm/internals.h | 8 ++++---- target/arm/cpu.c | 8 ++++---- target/arm/cpu32-stubs.c | 8 ++++---- target/arm/cpu64.c | 12 ++++++------ 4 files changed, 18 insertions(+), 18 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 3edc15c7b4a..00830b17248 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1750,10 +1750,10 @@ int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByteArray *buf, int reg); int aarch64_gdb_set_tag_ctl_reg(CPUState *cs, uint8_t *buf, int reg); int aarch64_gdb_get_tls_reg(CPUState *cs, GByteArray *buf, int reg); int aarch64_gdb_set_tls_reg(CPUState *cs, uint8_t *buf, int reg); -void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); -void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); -void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); -void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); +void aarch64_cpu_sve_finalize(ARMCPU *cpu, Error **errp); +void aarch64_cpu_sme_finalize(ARMCPU *cpu, Error **errp); +void aarch64_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); +void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); void aarch64_max_tcg_initfn(Object *obj); void aarch64_add_pauth_properties(Object *obj); void aarch64_add_sve_properties(Object *obj); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 76f5909e902..31e1fd6cd51 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1707,25 +1707,25 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) Error *local_err = NULL; if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - arm_cpu_sve_finalize(cpu, &local_err); + aarch64_cpu_sve_finalize(cpu, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); return; } - arm_cpu_sme_finalize(cpu, &local_err); + aarch64_cpu_sme_finalize(cpu, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); return; } - arm_cpu_pauth_finalize(cpu, &local_err); + aarch64_cpu_pauth_finalize(cpu, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); return; } - arm_cpu_lpa2_finalize(cpu, &local_err); + aarch64_cpu_lpa2_finalize(cpu, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); return; diff --git a/target/arm/cpu32-stubs.c b/target/arm/cpu32-stubs.c index 9e50bb1b0b5..d42b1a5d6a6 100644 --- a/target/arm/cpu32-stubs.c +++ b/target/arm/cpu32-stubs.c @@ -4,22 +4,22 @@ #include "target/arm/cpu.h" #include "target/arm/internals.h" -void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) +void aarch64_cpu_sme_finalize(ARMCPU *cpu, Error **errp) { g_assert_not_reached(); } -void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) +void aarch64_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { g_assert_not_reached(); } -void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) +void aarch64_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { g_assert_not_reached(); } -void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) +void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) { g_assert_not_reached(); } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index a93ad2da5ad..b38a78aac3f 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -60,7 +60,7 @@ int get_sysreg_idx(ARMSysRegs sysreg) #undef DEF -void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) +void aarch64_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { /* * If any vector lengths are explicitly enabled with sve properties, @@ -121,7 +121,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * Disable all SVE extensions as well. Note that some ZFR0 * fields are used also by SME so must not be wiped in * an SME-no-SVE config. We will clear the rest in - * arm_cpu_sme_finalize() if necessary. + * aarch_cpu_sme_finalize() if necessary. */ FIELD_DP64_IDREG(&cpu->isar, ID_AA64ZFR0, F64MM, 0); FIELD_DP64_IDREG(&cpu->isar, ID_AA64ZFR0, F32MM, 0); @@ -336,7 +336,7 @@ static void cpu_arm_set_sve(Object *obj, bool value, Error **errp) FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR0, SVE, value); } -void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) +void aarch64_cpu_sme_finalize(ARMCPU *cpu, Error **errp) { uint32_t vq_map = cpu->sme_vq.map; uint32_t vq_init = cpu->sme_vq.init; @@ -408,7 +408,7 @@ static void cpu_arm_set_sme(Object *obj, bool value, Error **errp) /* * For now, write 0 for "off" and 1 for "on" into the PFR1 field. * We will correct this value to report the right SME - * level (SME vs SME2) in arm_cpu_sme_finalize() later. + * level (SME vs SME2) in aarch_cpu_sme_finalize() later. */ FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR1, SME, value); } @@ -548,7 +548,7 @@ void aarch64_add_sme_properties(Object *obj) #endif } -void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) +void aarch64_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { ARMPauthFeature features = cpu_isar_feature(pauth_feature, cpu); ARMISARegisters *isar = &cpu->isar; @@ -666,7 +666,7 @@ void aarch64_add_pauth_properties(Object *obj) } } -void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) +void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) { uint64_t t; -- 2.53.0