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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-45d9e767cb9sm14697629f8f.2.2026.05.15.07.12.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 15 May 2026 07:12:53 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Richard Henderson , qemu-arm@nongnu.org, Joel Stanley , Kane Chen , Troy Lee , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier , Jamin Lin , Steven Lee , Andrew Jeffery , Manos Pitsidianakis Subject: [PATCH v6 19/20] target/arm: Build cpu32-system.o as common object Date: Fri, 15 May 2026 16:10:30 +0200 Message-ID: <20260515141032.3271-20-philmd@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260515141032.3271-1-philmd@linaro.org> References: <20260515141032.3271-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org cpu32.c only contains CPU types used in 32-bit system emulation: rename it as cpu32-system.c; always compile the file but only register the QOM types for the 32-bit binary. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/tcg/{cpu32.c => cpu32-system.c} | 19 ++++++------------- target/arm/tcg/meson.build | 5 +---- 2 files changed, 7 insertions(+), 17 deletions(-) rename target/arm/tcg/{cpu32.c => cpu32-system.c} (98%) diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32-system.c similarity index 98% rename from target/arm/tcg/cpu32.c rename to target/arm/tcg/cpu32-system.c index 8220d785f5b..51ed1f8f269 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32-system.c @@ -1,5 +1,5 @@ /* - * QEMU ARM TCG-only CPUs. + * QEMU ARM TCG-only CPUs (not needed for the AArch64 linux-user build) * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -10,18 +10,13 @@ #include "qemu/osdep.h" #include "qemu/units.h" +#include "qemu/target-info.h" #include "cpu.h" #include "accel/tcg/cpu-ops.h" #include "internals.h" -#if !defined(CONFIG_USER_ONLY) #include "hw/core/boards.h" -#endif #include "cpregs.h" - -/* CPU models. These are not needed for the AArch64 linux-user build. */ -#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) - static void arm926_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); @@ -738,13 +733,11 @@ static const ARMCPUInfo arm_tcg_cpus[] = { static void arm_tcg_cpu_register_types(void) { - size_t i; - - for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) { - arm_cpu_register(&arm_tcg_cpus[i]); + if (target_arm()) { + for (size_t i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) { + arm_cpu_register(&arm_tcg_cpus[i]); + } } } type_init(arm_tcg_cpu_register_types) - -#endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */ diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index f821331fbee..a6aac6deef0 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -29,10 +29,6 @@ translate32_d = [ arm_stubs_ss.add(files('stubs32.c')) -arm_ss.add(files( - 'cpu32.c', -)) - arm_ss.add(when: 'TARGET_AARCH64', if_true: gen_a64 + files( 'gengvec64.c', 'translate-a64.c', @@ -83,6 +79,7 @@ arm_common_user_system_ss.add(when: 'TARGET_AARCH64', if_true: files( arm_common_system_ss.add(files( 'cpregs-at.c', + 'cpu32-system.c', 'gicv5-cpuif.c', 'psci.c', 'tlb_helper.c', -- 2.53.0