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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48fe4c88495sm68165475e9.4.2026.05.15.07.11.02 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 15 May 2026 07:11:03 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Richard Henderson , qemu-arm@nongnu.org, Joel Stanley , Kane Chen , Troy Lee , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier , Jamin Lin , Steven Lee , Andrew Jeffery , Manos Pitsidianakis Subject: [PATCH v6 04/20] hw/arm/aspeed: Initialize 64-bit CPU types during DeviceRealize() Date: Fri, 15 May 2026 16:10:15 +0200 Message-ID: <20260515141032.3271-5-philmd@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260515141032.3271-1-philmd@linaro.org> References: <20260515141032.3271-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org aspeed_ast27x0.c models 2 similar SoC based on a 64-bit only CPU (Cortex-A35), only available in the 64-bit binary. If we build this file as common object, these SoCs become available in both 32 and 64-bit binaries; however when running the introspection test on the 32-bit binary, the init() method tries to init the Cortex-A35 type -- although not realizing it -- which is not available. This can be avoided by deferring the CPU type initialization to the SoC DeviceRealize step (this is safe because nothing uses the CPU type before, only the GIC access them, just after their realization). Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/aspeed_ast27x0.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 87dcb82e1b0..e50125bfeec 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -418,11 +418,6 @@ static void aspeed_soc_ast2700_init(Object *obj) g_assert_not_reached(); } - for (i = 0; i < sc->num_cpus; i++) { - object_initialize_child(obj, "cpu[*]", &a->cpu[i], - aspeed_soc_cpu_type(sc->valid_cpu_types)); - } - object_initialize_child(obj, "gic", &a->gic, gicv3_class_name()); object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU); @@ -701,6 +696,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) /* CPU */ for (i = 0; i < sc->num_cpus; i++) { + object_initialize_child(OBJECT(dev), "cpu[*]", &a->cpu[i], + aspeed_soc_cpu_type(sc->valid_cpu_types)); object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity", aspeed_calc_affinity(i), &error_abort); -- 2.53.0