From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7693FCD4F25 for ; Fri, 15 May 2026 15:40:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 25EA310F56A; Fri, 15 May 2026 15:40:54 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="SFM7e3WB"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 27A0510F56A for ; Fri, 15 May 2026 15:40:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1778859626; x=1810395626; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7KR356VUHv7B1YEvcMsqTOKP0Acf6NDw8c7I4WrDmsM=; b=SFM7e3WBLgrDX4XgNJP9c2CSUM06IgAWIsmRegnk8djgnRO2FqYNEcAM 0tJkyyaniNjMwIUuDqE39Uz9YuF8BqU2bTwQJVlW7RrXotCz/Bx3Hm+jo Y/BWkRoK/0e0JG6a06+GHkxs2ffzSFiDM/bJGNzX0tcSn889uSfFTSQvh uUbZCIDHPB0T75g0AIv5pJjzj4HVazbgvXCuJvDBG4qkuNLd8O1dGeGGe mYyUnz8+wcyscCfHzwsDY7g58V4OAVSnXlQYBkX2aW/0ErGKS1u6bsAgu gh+ZYIHkdeDEKdHa5GiKbfdRNE+SSnD3c8aDUGVDZAIJbMzNgTFo4sbNj g==; X-CSE-ConnectionGUID: TPEpaDljQ2ij5MRIwBjAeQ== X-CSE-MsgGUID: Xay2nlk4QG2f8Si75hOguA== X-IronPort-AV: E=McAfee;i="6800,10657,11787"; a="79936310" X-IronPort-AV: E=Sophos;i="6.23,236,1770624000"; d="scan'208";a="79936310" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 May 2026 08:40:26 -0700 X-CSE-ConnectionGUID: YzG8NHNURSWenKEBhrqTjw== X-CSE-MsgGUID: TZznVYMXRX2GeL9OJTOABg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,236,1770624000"; d="scan'208";a="242720008" Received: from jeevan-x299-aorus-gaming-3-pro.iind.intel.com ([10.227.90.91]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 May 2026 08:40:24 -0700 From: Jeevan B To: igt-dev@lists.freedesktop.org Cc: animesh.manna@intel.com, dibin.moolakadan.subrahmanian@intel.com, mohammed.thasleem@intel.com, ramanaidu.naladala@intel.com, Jeevan B Subject: [PATCH i-g-t v6 4/7] tests/kms_vrr: Add new test for DC3CO validation with LOBF Date: Fri, 15 May 2026 21:08:34 +0530 Message-ID: <20260515153838.841048-5-jeevan.b@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260515153838.841048-1-jeevan.b@intel.com> References: <20260515153838.841048-1-jeevan.b@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" Add lobf-dc3co subtest to validate DC3CO entry during link-off between frames. v2: Fix the flow logic. Signed-off-by: Jeevan B Reviewed-by: Mohammed Thasleem --- tests/kms_vrr.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/tests/kms_vrr.c b/tests/kms_vrr.c index 6043d40f1..82eb8554a 100644 --- a/tests/kms_vrr.c +++ b/tests/kms_vrr.c @@ -29,6 +29,7 @@ */ #include "igt.h" +#include "igt_pm.h" #include "igt_psr.h" #include "i915/intel_drrs.h" #include "sw_sync.h" @@ -76,6 +77,9 @@ * * SUBTEST: negative-basic * Description: Make sure that VRR should not be enabled on the Non-VRR panel. + * + * SUBTEST: lobf-dc3co + * Description: Test DC3CO entry during LOBF. */ #define NSECS_PER_SEC (1000000000ull) @@ -873,6 +877,25 @@ test_lobf(data_t *data, igt_crtc_t *crtc, igt_output_t *output, igt_assert_f(lobf_enabled, "LOBF not enabled\n"); } +static void test_lobf_dc3co(data_t *data, igt_crtc_t *crtc, + igt_output_t *output, uint32_t flags) +{ + unsigned long dc3co_count_before, dc3co_count_after; + + dc3co_count_before = igt_read_dc_counter(data->debugfs_fd, + IGT_INTEL_CHECK_DC3CO); + + test_lobf(data, crtc, output, flags); + + dc3co_count_after = igt_read_dc_counter(data->debugfs_fd, + IGT_INTEL_CHECK_DC3CO); + + igt_assert_f(dc3co_count_after > dc3co_count_before, + "DC3CO should be entered during link-off periods. " + "Before: %lu, After: %lu\n", + dc3co_count_before, dc3co_count_after); +} + static void test_cleanup(data_t *data, igt_crtc_t *crtc, igt_output_t *output) { igt_crtc_set_prop_value(crtc, @@ -1112,6 +1135,17 @@ int igt_main_args("drs:", long_opts, help_str, opt_handler, &data) run_vrr_test(&data, test_lobf, TEST_LINK_OFF); } + + igt_describe("This test validates DC3CO entry during LOBF (Link-Off Between " + "Frames) periods while VRR is active and PSR is disabled."); + + igt_subtest_with_dynamic("lobf-dc3co") { + igt_require(intel_display_ver(intel_get_drm_devid(data.drm_fd)) >= 35); + + igt_require_dc_counter(data.debugfs_fd, IGT_INTEL_CHECK_DC3CO); + + run_vrr_test(&data, test_lobf_dc3co, TEST_LINK_OFF); + } } igt_fixture() { -- 2.43.0