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From: sashiko-bot@kernel.org
To: "Manivannan Sadhasivam via B4 Relay"
	<devnull+manivannan.sadhasivam.oss.qualcomm.com@kernel.org>
Cc: linux-pci@vger.kernel.org
Subject: Re: [PATCH v8 5/5] misc: pci_endpoint_test: Add AER error handlers
Date: Mon, 18 May 2026 17:55:47 +0000	[thread overview]
Message-ID: <20260518175548.27E3DC2BCB7@smtp.kernel.org> (raw)
In-Reply-To: <20260518-pci-port-reset-v8-5-eb5a7d331dfc@oss.qualcomm.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Race condition in probe: pci_save_state() is called after misc_register()
--

commit 1e7c4e54131311f06f05246675701727353fa564
Author: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>

misc: pci_endpoint_test: Add AER error handlers

This commit adds AER error handlers to the PCI endpoint test driver.
It saves the PCI configuration state during probe and restores it
during a slot reset to ensure AER recovery succeeds.

> diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
> index dbd017cabbb92..3e89bd48c196b 100644
> --- a/drivers/misc/pci_endpoint_test.c
> +++ b/drivers/misc/pci_endpoint_test.c
> @@ -1327,6 +1327,8 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev,
>  		goto err_kfree_name;
>  	}
>  
> +	pci_save_state(pdev);
> +

Could this introduce a race condition with userspace?

Since misc_register() was just called above, the device node is already
accessible to userspace. If a userspace program immediately opens the device
and issues an ioctl like PCITEST_SET_IRQTYPE, it will trigger
pci_alloc_irq_vectors().

This could alter the PCI configuration space (such as modifying the PCI_COMMAND
register to set up MSI/MSI-X) before pci_save_state() executes.

If this happens, pci_save_state() would capture the modified state as the
baseline. During an AER recovery, pci_restore_state() would then restore
this modified state instead of the pristine hardware configuration.

Should pci_save_state() be called before misc_register() to ensure the base
configuration is correctly snapshotted?

>  	return 0;
>  
>  err_kfree_name:
> @@ -1448,12 +1450,33 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = {

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260518-pci-port-reset-v8-0-eb5a7d331dfc@oss.qualcomm.com?part=5

      reply	other threads:[~2026-05-18 17:55 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-18 14:59 [PATCH v8 0/5] PCI: Add support for resetting the Root Ports in a platform specific way Manivannan Sadhasivam via B4 Relay
2026-05-18 14:59 ` Manivannan Sadhasivam via B4 Relay
2026-05-18 14:59 ` Manivannan Sadhasivam
2026-05-18 14:59 ` [PATCH v8 1/5] PCI: dwc: ep: Clear MSI iATU mapping in dw_pcie_ep_cleanup() Manivannan Sadhasivam via B4 Relay
2026-05-18 14:59   ` Manivannan Sadhasivam via B4 Relay
2026-05-18 14:59   ` Manivannan Sadhasivam
2026-05-18 16:04   ` sashiko-bot
2026-05-18 14:59 ` [PATCH v8 2/5] PCI/ERR: Add support for resetting the Root Ports in a platform specific way Manivannan Sadhasivam via B4 Relay
2026-05-18 14:59   ` Manivannan Sadhasivam via B4 Relay
2026-05-18 14:59   ` Manivannan Sadhasivam
2026-05-18 16:27   ` sashiko-bot
2026-05-18 14:59 ` [PATCH v8 3/5] PCI: host-common: Add link down handling for Root Ports Manivannan Sadhasivam via B4 Relay
2026-05-18 14:59   ` Manivannan Sadhasivam via B4 Relay
2026-05-18 14:59   ` Manivannan Sadhasivam
2026-05-18 17:05   ` sashiko-bot
2026-05-18 14:59 ` [PATCH v8 4/5] PCI: qcom: Add support for resetting the Root Port due to link down event Manivannan Sadhasivam via B4 Relay
2026-05-18 14:59   ` Manivannan Sadhasivam via B4 Relay
2026-05-18 14:59   ` Manivannan Sadhasivam
2026-05-18 17:38   ` sashiko-bot
2026-05-18 14:59 ` [PATCH v8 5/5] misc: pci_endpoint_test: Add AER error handlers Manivannan Sadhasivam via B4 Relay
2026-05-18 14:59   ` Manivannan Sadhasivam via B4 Relay
2026-05-18 14:59   ` Manivannan Sadhasivam
2026-05-18 17:55   ` sashiko-bot [this message]

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