[PATCH 0/5] drm/amdgpu/uvd: Fix UVD BO memory placement issues

["Timur Kristóf" <timur.kristof@gmail.com>]

UVD 4.x and older have two requirements for CS BOs:
1. All BOs must not cross 256M segments
2. MSG and FB BOs must be located in the same segment as the VCPU BO

The amdgpu_uvd code attempts to solve those requirements,
but unfortunately it has hit various limitations:

* VCPU BO may be placed in a different segment
* VRAM allocations may cross 256M in low memory scenarios
* GTT manager doesn't respect placement requirements
* GTT allocations may cross 256M
* GTT->GTT moves are not implemented

Let's solve these issues by fixing the GTT manager,
making sure that GTT allocations are placed in 256M segments
and VRAM allocations are moved to GTT when they cross 256M.
It also fixes forcing MSG and FB BOs to the UVD segment
when the UVD segment isn't the first segment, which can be
the case when resizable BAR is enabled.

This series should be backported to 7.0 and 7.1 because
technically this may have been a regression for some users
caused by switching to amdgpu by default.

Timur Kristóf (5):
  drm/amdgpu: Respect placement requirements in amdgpu_gtt_mgr functions
  drm/amdgpu: Use placements of 256M GART segments for SI/CIK
  drm/amdgpu/uvd: Place VCPU BO only in VRAM for UVD 4.x and older
  drm/amdgpu/uvd: Fix forcing BOs into UVD segment when it isn't at 0
  drm/amdgpu/uvd: Move BOs to GTT when we can't place them in VRAM
    correctly

 drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 30 ++++++++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c     | 57 ++++++++++++++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h     |  3 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c     | 74 +++++++++++++++------
 4 files changed, 136 insertions(+), 28 deletions(-)

-- 
2.54.0