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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48febe74a53sm103879765e9.27.2026.05.19.02.06.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 May 2026 02:06:07 -0700 (PDT) Date: Tue, 19 May 2026 10:06:06 +0100 From: David Laight To: Mikhail Gavrilov Cc: Leon Romanovsky , m.szyprowski@samsung.com, hch@lst.de, robin.murphy@arm.com, djbw@kernel.org, akpm@linux-foundation.org, catalin.marinas@arm.com, harry@kernel.org, ming.lei@redhat.com, iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH] dma-debug: skip cacheline overlap tracking on cache-coherent architectures Message-ID: <20260519100606.6b3c91e3@pumpkin> In-Reply-To: References: <20260518113251.64844-1-mikhail.v.gavrilov@gmail.com> <20260518121047.GR33515@unreal> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On Mon, 18 May 2026 17:23:15 +0500 Mikhail Gavrilov wrote: > On Mon, May 18, 2026 at 5:10=E2=80=AFPM Leon Romanovsky = wrote: > > > > I would say this reproducer is incorrect. From what I recall, the only = two > > legitimate use cases for cacheline overlap are virtio and RDMA. =20 >=20 > The wild trace in the commit message is NVMe block I/O -- neither virtio > nor RDMA: >=20 > add_dma_entry -> debug_dma_map_phys -> dma_map_phys -> > blk_dma_map_iter_start -> nvme_map_data >=20 > The block layer submits many concurrent in-flight requests; small > kmalloc'd buffers naturally land in the same cacheline under high IOPS, Isn't there a flag to kmalloc() that indicates the buffers will be used for dma and mustn't share a cache line with anything else writable. (Which means the size must be rounded up to a multiple of the cache line size.) For DMA_FROM_DEVICE it is important that the cpu doesn't dirty the cache lines. This is probably worse on systems with 256 byte cache lines. -- David > which is incidental rather than intentional overlap. Ming Lei's report > linked in the commit message [1] enumerates additional non-virtio / > non-RDMA cases hitting the same WARN: liburing iopoll tests, raid1, > dm-thin and other storage utilities. >=20 > > The first intentionally relies on it for small allocations, and the sec= ond exports the > > cachelines to the user space and cannot operate on non=E2=80=91coherent= architectures. =20 >=20 > The reproducer isn't claiming to be either of those. It deterministically > reaches the same state-based gate the wild NVMe trace hits > (!is_cache_clean && overlap > 7, with direction !=3D DMA_TO_DEVICE, after > the v2 coherent-arch / SWIOTLB-bounce suppressions are evaluated). Since > that gate has no subsystem-specific term, any caller -- synthetic or real > -- reaching it with those state values triggers the same WARN. >=20 > If the broader concern is that the block layer should opt into your > coherency-attribute work rather than relying on debug-side suppression, > that's a reasonable longer-term direction. But it's additive: even with > opt-in adoption, the WARN remains a false positive on coherent arches > for callers that don't annotate -- which is exactly what v2 (3d48c9fd78dd) > already established for the sibling "cacheline tracking EEXIST" err_print= k. >=20 > [1] https://lore.kernel.org/all/ZwxzdWmYcBK27mUs@fedora/ >=20