From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC7B3348C43 for ; Tue, 19 May 2026 13:30:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779197419; cv=none; b=J8JVggYaX3KhBAg8xWOQK5Y62Tr6D4e0tCO2KnkZb/JsYKECeBE6tc25YIGG0tb2Npn5M8doqVfaLm/oT8nEORhm+z5wqcLDm1Nkvb3RzRGOb5y4VfTnqQyvuTaaQWUXGI5YKEFNm5Q5f+cekD1e5DACmWsiahXeWFqTxaog10c= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779197419; c=relaxed/simple; bh=UzOZQx27CdLGBENI1mpYn4b5sag6RELaqRo18zF7V40=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:content-type; b=iONHY+3Y87hjA7ejAU1l0s/UZwc1RS2iqJ4agF6LU2VQShrgx7vas3OtfPbMYMDxoXMiekfX1LNg56U+6+qjWdPwXV8Pw27Njc7OWIf8EhEJhj4LHNzijE3YHzDQR7BgYPGBYcWD1Ny/s7bsghGKuR7srdFvQayfL7fJOmDOZaA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=Rz/VEOb5; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="Rz/VEOb5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1779197417; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=czRYnC1h5hxho7j5XY+hTvhhizrNmuKL0vpohSAAF5c=; b=Rz/VEOb5p6fyaoRCs4AemdVKkOmBGqS/8ULjMiTt88jU0T+4T7mkZBVj5RtHEviv4jaVSs qk6STX175uxLfMohmwe3nQbBRIGroRPCa5+Tzcq6tTmnBTlmn9bppO2piKlCcG75UdQMjC rNFyDQHtrI+yXSfR96eUezot3lTHzdw= Received: from mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-548-FOkC3wPlMLS1hGClBjlfiA-1; Tue, 19 May 2026 09:30:13 -0400 X-MC-Unique: FOkC3wPlMLS1hGClBjlfiA-1 X-Mimecast-MFC-AGG-ID: FOkC3wPlMLS1hGClBjlfiA_1779197409 Received: from mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.111]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 909AB19560B8; Tue, 19 May 2026 13:30:09 +0000 (UTC) Received: from laptop.redhat.com (unknown [10.44.49.207]) by mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id A843C1800576; Tue, 19 May 2026 13:30:03 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v5 08/18] target/arm/cpu_idregs: generate tables for Arm64 ID registers and fields Date: Tue, 19 May 2026 15:27:22 +0200 Message-ID: <20260519132905.145643-9-eric.auger@redhat.com> In-Reply-To: <20260519132905.145643-1-eric.auger@redhat.com> References: <20260519132905.145643-1-eric.auger@redhat.com> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 X-Mimecast-MFC-PROC-ID: gbFqaB78bBEz0sLiKmHti57aqk0Jc27vVVIMInf64R0_1779197409 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: 8bit content-type: text/plain; charset="US-ASCII"; x-default=true From: Shaju Abraham Include cpu-idregs.h.inc multiple times with different definitions for the X-macros. This will generate tables for all Arm64 ID registers and their fields. Additionally, initialize the tables with all architecturally defined values. These tables will be consumed by the property layer in future patches. Co-authored-by: Khushit Shah Signed-off-by: Shaju Abraham Signed-off-by: Eric Auger --- target/arm/cpu-idregs.c | 50 +++++++++++++++++++++++++++++++++++++++++ target/arm/meson.build | 1 + 2 files changed, 51 insertions(+) create mode 100644 target/arm/cpu-idregs.c diff --git a/target/arm/cpu-idregs.c b/target/arm/cpu-idregs.c new file mode 100644 index 0000000000..f79b22680c --- /dev/null +++ b/target/arm/cpu-idregs.c @@ -0,0 +1,50 @@ +/* + * ARM ID register field table. + * + * Builds the per-id-register field descriptor arrays and the global + * arm_idregs[] table. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "cpu.h" +#include "cpu-idregs.h" + +#define IDREG_START(reg) \ + static ARM64SysRegField reg##_fields[] = { + +#define IDREG_END(reg) \ + }; + +#define IDREG_FIELD(reg, field, _shift, _length) \ + { \ + .name = #field, \ + .index = reg##_IDX, \ + .shift = (_shift), \ + .length = (_length), \ + }, +#include "cpu-idregs.h.inc" +#undef IDREG_START +#undef IDREG_END +#undef IDREG_FIELD + +/* generate an array of top level ID registers */ +#define IDREG_END(reg) +#define IDREG_FIELD(reg, field, shift, length) + +#define IDREG_START(reg) \ + [reg##_IDX] = { \ + .name = #reg, \ + .index = reg##_IDX, \ + .fields = reg##_fields, \ + .fields_count = ARRAY_SIZE(reg##_fields), \ + }, + +ARM64SysReg arm64_id_regs[NUM_ID_IDX] = { +#include "cpu-idregs.h.inc" +}; +#undef IDREG_START +#undef IDREG_END +#undef IDREG_FIELD diff --git a/target/arm/meson.build b/target/arm/meson.build index 4723f9f170..64d1ec63ab 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -19,6 +19,7 @@ arm_common_ss.add(files( arm_common_system_ss.add(files( 'arm-qmp-cmds.c', + 'cpu-idregs.c', )) arm_system_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c')) arm_system_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c')) -- 2.53.0