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Tsirkin" To: Djordje Todorovic Cc: "qemu-devel@nongnu.org" , "qemu-riscv@nongnu.org" , "cfu@mips.com" , "marcel.apfelbaum@gmail.com" , "dbarboza@ventanamicro.com" , "philmd@linaro.org" , "alistair23@gmail.com" , "thuth@redhat.com" Subject: Re: [PATCH v9 0/7] Add RISC-V big-endian target support Message-ID: <20260520101034-mutt-send-email-mst@kernel.org> References: <20260511083819.206216-1-djordje.todorovic@htecgroup.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260511083819.206216-1-djordje.todorovic@htecgroup.com> Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, May 11, 2026 at 08:38:26AM +0000, Djordje Todorovic wrote: > Rebase on top of master. is Linux going to support this, ever? given this history: https://lore.kernel.org/lkml/CAHk-%3DwgYcOiFvsJzFb%2BHfB4n6Wj6zM5H5EghUMfpXSCzyQVSfA@mail.gmail.com/t/#mce138059dc56014643bbda330810183031ef5c06 pls include a cover letter explaining why we should bother with this. > Djordje Todorovic (7): > target/riscv: Define MSTATUS_SBE and MSTATUS_MBE bit masks > target/riscv: Add big-endian CPU configuration field and reset logic > target/riscv: Implement runtime data endianness via MSTATUS bits > hw/riscv: Make boot code endianness-aware at runtime > target/riscv: Fix page table walk endianness for big-endian harts > target/riscv: Expose big-endian CPU property and add documentation > target/riscv: Add endianness test for RISC-V BE > > docs/system/target-riscv.rst | 24 ++++++ > hw/riscv/boot.c | 81 ++++++++++++++++--- > include/hw/riscv/boot.h | 1 + > target/riscv/cpu.c | 11 +-- > target/riscv/cpu.h | 23 ++++++ > target/riscv/cpu_bits.h | 2 + > target/riscv/cpu_cfg_fields.h.inc | 1 + > target/riscv/cpu_helper.c | 28 +++++-- > target/riscv/insn_trans/trans_rva.c.inc | 4 +- > target/riscv/insn_trans/trans_rvd.c.inc | 4 +- > target/riscv/insn_trans/trans_rvf.c.inc | 4 +- > target/riscv/insn_trans/trans_rvi.c.inc | 8 +- > target/riscv/insn_trans/trans_rvzacas.c.inc | 4 +- > target/riscv/insn_trans/trans_rvzalasr.c.inc | 4 +- > target/riscv/insn_trans/trans_rvzce.c.inc | 4 +- > target/riscv/insn_trans/trans_rvzfh.c.inc | 4 +- > target/riscv/insn_trans/trans_rvzicfiss.c.inc | 4 +- > target/riscv/insn_trans/trans_xmips.c.inc | 8 +- > target/riscv/insn_trans/trans_xthead.c.inc | 16 ++-- > target/riscv/insn_trans/trans_zilsd.c.inc | 4 +- > target/riscv/internals.h | 9 +-- > target/riscv/tcg/tcg-cpu.c | 3 + > target/riscv/translate.c | 22 ++--- > tests/functional/riscv64/meson.build | 1 + > tests/functional/riscv64/test_endianness.py | 57 +++++++++++++ > 25 files changed, 251 insertions(+), 80 deletions(-) > create mode 100644 tests/functional/riscv64/test_endianness.py > > -- > 2.34.1