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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-45eaa7d0a36sm4184810f8f.2.2026.05.21.10.55.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 10:55:33 -0700 (PDT) Date: Thu, 21 May 2026 18:55:32 +0100 From: David Laight To: Yang Shi Cc: Heiko Carstens , Alexander Gordeev , Sven Schnelle , Vasily Gorbik , Christian Borntraeger , Juergen Christ , "Christoph Lameter (Ampere)" , Peter Zijlstra , Shrikanth Hegde , linux-kernel@vger.kernel.org, linux-s390@vger.kernel.org Subject: Re: [PATCH v3 0/9] s390: Improve this_cpu operations Message-ID: <20260521185532.002541c6@pumpkin> In-Reply-To: <592ea7fb-b836-4c47-a0cb-248a185cbaa8@os.amperecomputing.com> References: <20260520092243.264847-1-hca@linux.ibm.com> <9d503c6f-5641-4b28-998e-01e38b3622a9@os.amperecomputing.com> <20260520233409.0683f595@pumpkin> <20260521111744.6e58bfd6@pumpkin> <592ea7fb-b836-4c47-a0cb-248a185cbaa8@os.amperecomputing.com> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: linux-s390@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Thu, 21 May 2026 09:57:37 -0700 Yang Shi wrote: > On 5/21/26 3:17 AM, David Laight wrote: > > On Wed, 20 May 2026 17:23:37 -0700 > > Yang Shi wrote: > > > >> On 5/20/26 3:34 PM, David Laight wrote: > > ... > >>> But I'm sure I remember that some cpu don't like having the same > >>> physical address at different virtual addresses (and not just those > >>> with VIVT caches like some sparc cpu). > >> Yeah, VIVT cache doesn't like it due to cache alias. But the mapping is > >> really percpu, so the mapping to the physical address belonging to > >> another CPU should never pollute the current CPU's cache if I don't miss > >> something. > >> > >>> I'm sure code can end up accessing the current cpu's percpu data > >>> using the same address that other cpu use - there are definitely > >>> places where it needs that address. > >> No, it is not. In the percpu page table approach, we use different > >> address for this_cpu_*() and per_cpu_ptr() which is mainly used to > >> initialize percpu data for all CPUs. > > You missed something. > > > > Look, for example, at kernel/locking/osq_lock.c > > The code uses this_cpu_ptr() and then both dereferences the pointer > > and writes it to places that other cpu will use. > > It also uses per_cpu_ptr() to get an address it can use for the per-cpu > > data of another cpu. > > (That code all assumes preemption is disabled.) > > this_cpu_ptr() uses different addresses for different CPUs. It is a > special case, it is not due to VIVT, but because it may confuse list > API. Because list API determines list is empty by comparing pointers > (head->next == head). this_cpu_read/write/add/sub, etc, are fine. But you could quite easily get code that manages to mix accesses through this_cpu_ptr() with direct accesses to per-cpu variables in the same cache line. I'm sure some arm cpu really don't like you doing that. (But it is a foggy memory from somewhere.) You can use per-cpu page tables, but it really only helps for a few items. Anything that is RMW (eg add on pretty much everything except x86) either has to disable preemption or use a compare and exchange loop. Variables like 'current' can be written into the per-cpu page table data area by the process switch code (as I believe s390 does). The 'trick' here will work for reading/writing values if you don't care that the value read is stale (or might have been written to the memory for a different cpu). It might work for updating the preemption disable count - because you can only be preempted while it is zero. -- David > > And per_cpu_ptr() also uses different addresses for different CPUs. > > The lwn article explained it. > https://lwn.net/SubscriberLink/1073395/12c08f128e515809/ > > Thanks, > Yang > > > > > -- David > > > >> Thanks, > >> Yang >