From: Arnd Bergmann <arnd@kernel.org>
To: Ingo Molnar <mingo@redhat.com>
Cc: Arnd Bergmann <arnd@arndb.de>,
Richard Weinberger <richard@nod.at>,
Anton Ivanov <anton.ivanov@cambridgegreys.com>,
Johannes Berg <johannes@sipsolutions.net>,
Thomas Gleixner <tglx@kernel.org>, Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
"H. Peter Anvin" <hpa@zytor.com>,
Peter Zijlstra <peterz@infradead.org>,
Will Deacon <will@kernel.org>, Boqun Feng <boqun@kernel.org>,
Gary Guo <gary@garyguo.net>, Yury Norov <yury.norov@gmail.com>,
Rasmus Villemoes <linux@rasmusvillemoes.dk>,
Boris Ostrovsky <boris.ostrovsky@oracle.com>,
Alexander Usyskin <alexander.usyskin@intel.com>,
Tony Nguyen <anthony.l.nguyen@intel.com>,
Przemek Kitszel <przemyslaw.kitszel@intel.com>,
x86@kernel.org, linux-kernel@vger.kernel.org,
linux-um@lists.infradead.org
Subject: [PATCH 7/8] x86: remove dependencies on per-CPU options
Date: Fri, 22 May 2026 16:19:58 +0200 [thread overview]
Message-ID: <20260522141959.1071595-8-arnd@kernel.org> (raw)
In-Reply-To: <20260522141959.1071595-1-arnd@kernel.org>
From: Arnd Bergmann <arnd@arndb.de>
A few CPU feature options are defined in terms of CONFIG_Mxxx
CPU selection options.
This conflicts with the idea of CONFIG_X86_GENERIC allowing
one to build a kernel that works with multiple slightly
incompatible CPUs.
As a simplification, change all of these to be enabled in terms
of either 586-class or 686-class builds.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/x86/Kconfig.cpu | 14 ++++----------
arch/x86/Kconfig.cpufeatures | 8 +-------
arch/x86/include/asm/bitops.h | 4 ++--
arch/x86/include/asm/debugreg.h | 10 ++++------
arch/x86/include/asm/ptrace.h | 6 +-----
5 files changed, 12 insertions(+), 30 deletions(-)
diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index 4991b633047e..979db473a41d 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -242,8 +242,7 @@ config X86_L1_CACHE_SHIFT
default "6"
config X86_F00F_BUG
- def_bool y
- depends on M586MMX || M586TSC || M586
+ def_bool X86_MINIMUM_CPU_FAMILY=5 && CPU_SUP_INTEL
config X86_ALIGNMENT_16
def_bool y
@@ -264,12 +263,6 @@ config X86_HAVE_PAE
def_bool y
depends on MCRUSOE || MEFFICEON || MCYRIXIII || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC7 || MATOM || X86_64
-# this should be set for all -march=.. options where the compiler
-# generates cmov.
-config X86_CMOV
- def_bool y
- depends on (MK7 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || MATOM || MGEODE_LX || X86_64)
-
config X86_MINIMUM_CPU_FAMILY
int
default "64" if X86_64
@@ -278,7 +271,8 @@ config X86_MINIMUM_CPU_FAMILY
config X86_DEBUGCTLMSR
def_bool y
- depends on !(MK6 || MCYRIXIII || M586MMX || M586TSC || M586) && !UML
+ depends on !UML
+ depends on X86_MINIMUM_CPU_FAMILY=6
config IA32_FEAT_CTL
def_bool y
@@ -314,7 +308,7 @@ config CPU_SUP_INTEL
config CPU_SUP_CYRIX_32
default y
bool "Support Cyrix processors" if PROCESSOR_SELECT
- depends on M586 || M586TSC || M586MMX || (EXPERT && !64BIT)
+ depends on X86_MINIMUM_CPU_FAMILY=5
help
This enables detection, tunings and quirks for Cyrix processors
diff --git a/arch/x86/Kconfig.cpufeatures b/arch/x86/Kconfig.cpufeatures
index e0f2ff65377d..a0a1e838014d 100644
--- a/arch/x86/Kconfig.cpufeatures
+++ b/arch/x86/Kconfig.cpufeatures
@@ -44,13 +44,7 @@ config X86_REQUIRED_FEATURE_NOPL
# generates cmov.
config X86_REQUIRED_FEATURE_CMOV
def_bool y
- depends on X86_CMOV
-
-# this should be set for all -march= options where the compiler
-# generates movbe.
-config X86_REQUIRED_FEATURE_MOVBE
- def_bool y
- depends on MATOM
+ depends on X86_MINIMUM_CPU_FAMILY >= 6
config X86_REQUIRED_FEATURE_SYSFAST32
def_bool y
diff --git a/arch/x86/include/asm/bitops.h b/arch/x86/include/asm/bitops.h
index c2ce213f2b9b..f65872f67820 100644
--- a/arch/x86/include/asm/bitops.h
+++ b/arch/x86/include/asm/bitops.h
@@ -312,7 +312,7 @@ static __always_inline __attribute_const__ int variable_ffs(int x)
asm("bsfl %1,%0"
: "=r" (r)
: ASM_INPUT_RM (x), "0" (-1));
-#elif defined(CONFIG_X86_CMOV)
+#elif CONFIG_X86_MINIMUM_CPU_FAMILY >= 6
asm("bsfl %1,%0\n\t"
"cmovzl %2,%0"
: "=&r" (r) : "rm" (x), "r" (-1));
@@ -369,7 +369,7 @@ static __always_inline __attribute_const__ int fls(unsigned int x)
asm("bsrl %1,%0"
: "=r" (r)
: ASM_INPUT_RM (x), "0" (-1));
-#elif defined(CONFIG_X86_CMOV)
+#elif CONFIG_X86_MINIMUM_CPU_FAMILY >= 6
asm("bsrl %1,%0\n\t"
"cmovzl %2,%0"
: "=&r" (r) : "rm" (x), "rm" (-1));
diff --git a/arch/x86/include/asm/debugreg.h b/arch/x86/include/asm/debugreg.h
index a2c1f2d24b64..3799b2bb27bc 100644
--- a/arch/x86/include/asm/debugreg.h
+++ b/arch/x86/include/asm/debugreg.h
@@ -176,10 +176,9 @@ static inline unsigned long get_debugctlmsr(void)
{
unsigned long debugctlmsr = 0;
-#ifndef CONFIG_X86_DEBUGCTLMSR
- if (boot_cpu_data.x86 < 6)
+ if (CONFIG_X86_MINIMUM_CPU_FAMILY < 6 || boot_cpu_data.x86 < 6)
return 0;
-#endif
+
rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
return debugctlmsr;
@@ -187,10 +186,9 @@ static inline unsigned long get_debugctlmsr(void)
static inline void update_debugctlmsr(unsigned long debugctlmsr)
{
-#ifndef CONFIG_X86_DEBUGCTLMSR
- if (boot_cpu_data.x86 < 6)
+ if (CONFIG_X86_MINIMUM_CPU_FAMILY < 6 || boot_cpu_data.x86 < 6)
return;
-#endif
+
wrmsrq(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
}
diff --git a/arch/x86/include/asm/ptrace.h b/arch/x86/include/asm/ptrace.h
index 7bb7bd90355d..b1d881229fab 100644
--- a/arch/x86/include/asm/ptrace.h
+++ b/arch/x86/include/asm/ptrace.h
@@ -449,11 +449,7 @@ static inline unsigned long regs_get_kernel_argument(struct pt_regs *regs,
}
#define arch_has_single_step() (1)
-#ifdef CONFIG_X86_DEBUGCTLMSR
-#define arch_has_block_step() (1)
-#else
-#define arch_has_block_step() (boot_cpu_data.x86 >= 6)
-#endif
+#define arch_has_block_step() ((CONFIG_X86_MINIMUM_CPU_FAMILY >= 6) || (boot_cpu_data.x86 >= 6))
#define ARCH_HAS_USER_SINGLE_STEP_REPORT
--
2.39.5
next prev parent reply other threads:[~2026-05-22 14:20 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-22 14:19 [PATCH 0/8] x86-32 CPU configuration cleanups Arnd Bergmann
2026-05-22 14:19 ` [PATCH 1/8] x86: remove ts5500 platforms support Arnd Bergmann
2026-06-01 8:31 ` Geert Uytterhoeven
2026-06-01 12:27 ` Arnd Bergmann
2026-05-22 14:19 ` [PATCH 2/8] x86: remove AMD Élan remnants Arnd Bergmann
2026-05-22 14:19 ` [PATCH 3/8] x86: make TSC usage unconditional Arnd Bergmann
2026-05-22 16:11 ` Brian Gerst
2026-05-22 14:19 ` [PATCH 4/8] x86: make CX8 " Arnd Bergmann
2026-05-22 14:19 ` [PATCH 5/8] x86: remove dependencies on CONFIG_M... CPU options Arnd Bergmann
2026-05-22 15:46 ` Juergen Gross
2026-05-22 18:54 ` Arnd Bergmann
2026-05-22 19:00 ` Jürgen Groß
2026-05-22 21:22 ` David Laight
2026-05-22 14:19 ` [PATCH 6/8] x86: require minimum 64 byte cache lines Arnd Bergmann
2026-05-22 14:19 ` Arnd Bergmann [this message]
2026-05-22 14:19 ` [PATCH 8/8] x86: simplify 32-bit instruction set selection Arnd Bergmann
2026-05-22 21:33 ` David Laight
2026-05-23 8:51 ` Arnd Bergmann
2026-05-23 10:02 ` David Laight
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