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Tsirkin" , Paolo Bonzini , Richard Henderson , Ani Sinha , Alexander Gryanko Subject: [PATCH 1/3] hw/i386/pc: Introduce 11.2 machine type for SMBIOS type 8 base migration Date: Sat, 23 May 2026 06:41:56 +0300 Message-Id: <20260523034158.57487-2-xpahos@gmail.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20260523034158.57487-1-xpahos@gmail.com> References: <20260523034158.57487-1-xpahos@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::12a; envelope-from=xpahos@gmail.com; helo=mail-lf1-x12a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sat, 23 May 2026 08:49:35 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org SMBIOS Type 8 (Port Connector) tables have been using T0_BASE (0x0) for handle allocation, which can collide with handles assigned to other SMBIOS types. Types 2, 3, 4, 9, and 11 already use dedicated ranges (T2_BASE=0x200, T3_BASE=0x300, etc.). Introduce pc-q35-11.2 and pc-i440fx-11.2 with smbios_type8_handle_t8_base enabled, so Type 8 handles start at 0x800. The 11.1 machine types retain T0_BASE for migration compatibility. Other platforms (ARM, LoongArch, RISC-V) are not changed by this patch. Signed-off-by: Alexander Gryanko --- hw/core/machine.c | 3 +++ hw/i386/pc.c | 3 +++ hw/i386/pc_piix.c | 16 ++++++++++++++-- hw/i386/pc_q35.c | 16 ++++++++++++++-- include/hw/core/boards.h | 3 +++ include/hw/i386/pc.h | 4 ++++ 6 files changed, 41 insertions(+), 4 deletions(-) diff --git a/hw/core/machine.c b/hw/core/machine.c index 63baff859f..96de2d20f0 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -39,6 +39,9 @@ #include "hw/acpi/generic_event_device.h" #include "qemu/audio.h" +GlobalProperty hw_compat_11_1[] = {}; +const size_t hw_compat_11_1_len = G_N_ELEMENTS(hw_compat_11_1); + GlobalProperty hw_compat_11_0[] = { { "chardev-vc", "encoding", "cp437" }, }; diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 2ecad3c503..17ad8b6489 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -73,6 +73,9 @@ #include "hw/xen/xen-bus.h" #endif +GlobalProperty pc_compat_11_1[] = {}; +const size_t pc_compat_11_1_len = G_N_ELEMENTS(pc_compat_11_1); + GlobalProperty pc_compat_11_0[] = {}; const size_t pc_compat_11_0_len = G_N_ELEMENTS(pc_compat_11_0); diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 82457bdb16..27e1d552f6 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -406,6 +406,7 @@ static void pc_i440fx_machine_options(MachineClass *m) pcmc->default_south_bridge = TYPE_PIIX3_DEVICE; pcmc->pci_root_uid = 0; pcmc->default_cpu_version = 1; + pcmc->smbios_type8_handle_t8_base = true; m->family = "pc_piix"; m->desc = "Standard PC (i440FX + PIIX, 1996)"; @@ -428,12 +429,23 @@ static void pc_i440fx_machine_options(MachineClass *m) pc_piix_compat_defaults, pc_piix_compat_defaults_len); } -static void pc_i440fx_machine_11_1_options(MachineClass *m) +static void pc_i440fx_machine_11_2_options(MachineClass *m) { pc_i440fx_machine_options(m); } -DEFINE_I440FX_MACHINE_AS_LATEST(11, 1); +DEFINE_I440FX_MACHINE_AS_LATEST(11, 2); + +static void pc_i440fx_machine_11_1_options(MachineClass *m) +{ + PCMachineClass *pcmc = PC_MACHINE_CLASS(m); + pc_i440fx_machine_11_2_options(m); + pcmc->smbios_type8_handle_t8_base = false; + compat_props_add(m->compat_props, hw_compat_11_1, hw_compat_11_1_len); + compat_props_add(m->compat_props, pc_compat_11_1, pc_compat_11_1_len); +} + +DEFINE_I440FX_MACHINE(11, 1); static void pc_i440fx_machine_11_0_options(MachineClass *m) { diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index d8fed698c7..cf1ae9b78b 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -345,6 +345,7 @@ static void pc_q35_machine_options(MachineClass *m) PCMachineClass *pcmc = PC_MACHINE_CLASS(m); pcmc->pci_root_uid = 0; pcmc->default_cpu_version = 1; + pcmc->smbios_type8_handle_t8_base = true; m->family = "pc_q35"; m->desc = "Standard PC (Q35 + ICH9, 2009)"; @@ -365,12 +366,23 @@ static void pc_q35_machine_options(MachineClass *m) pc_q35_compat_defaults, pc_q35_compat_defaults_len); } -static void pc_q35_machine_11_1_options(MachineClass *m) +static void pc_q35_machine_11_2_options(MachineClass *m) { pc_q35_machine_options(m); } -DEFINE_Q35_MACHINE_AS_LATEST(11, 1); +DEFINE_Q35_MACHINE_AS_LATEST(11, 2); + +static void pc_q35_machine_11_1_options(MachineClass *m) +{ + PCMachineClass *pcmc = PC_MACHINE_CLASS(m); + pc_q35_machine_11_2_options(m); + pcmc->smbios_type8_handle_t8_base = false; + compat_props_add(m->compat_props, hw_compat_11_1, hw_compat_11_1_len); + compat_props_add(m->compat_props, pc_compat_11_1, pc_compat_11_1_len); +} + +DEFINE_Q35_MACHINE(11, 1); static void pc_q35_machine_11_0_options(MachineClass *m) { diff --git a/include/hw/core/boards.h b/include/hw/core/boards.h index 29c68931d8..a436d48c8e 100644 --- a/include/hw/core/boards.h +++ b/include/hw/core/boards.h @@ -815,6 +815,9 @@ compat_props_add(GPtrArray *arr, } } +extern GlobalProperty hw_compat_11_1[]; +extern const size_t hw_compat_11_1_len; + extern GlobalProperty hw_compat_11_0[]; extern const size_t hw_compat_11_0_len; diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 85a74363b5..b7d21fb96e 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -102,6 +102,7 @@ struct PCMachineClass { /* SMBIOS compat: */ bool smbios_defaults; bool smbios_legacy_mode; + bool smbios_type8_handle_t8_base; SmbiosEntryPointType default_smbios_ep_type; /* RAM / address space compat: */ @@ -208,6 +209,9 @@ void pc_system_parse_ovmf_flash(uint8_t *flash_ptr, size_t flash_size); /* sgx.c */ void pc_machine_init_sgx_epc(PCMachineState *pcms); +extern GlobalProperty pc_compat_11_1[]; +extern const size_t pc_compat_11_1_len; + extern GlobalProperty pc_compat_11_0[]; extern const size_t pc_compat_11_0_len; -- 2.39.5 (Apple Git-154)