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Mon, 25 May 2026 05:30:41 +0000 From: Jamin Lin To: =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Kane Chen , Andrew Jeffery , Joel Stanley , Pierrick Bouvier , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: Jamin Lin , Troy Lee Subject: [PATCH v2 2/9] hw/arm/aspeed: Convert SRAM size definition to array type Thread-Topic: [PATCH v2 2/9] hw/arm/aspeed: Convert SRAM size definition to array type Thread-Index: AQHc7Aeg/P2uptVnAke6Q2f5p4gAdA== Date: Mon, 25 May 2026 05:30:40 +0000 Message-ID: <20260525053036.3305181-3-jamin_lin@aspeedtech.com> References: <20260525053036.3305181-1-jamin_lin@aspeedtech.com> In-Reply-To: <20260525053036.3305181-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: TYPPR06MB8206:EE_|TYZPR06MB6657:EE_ x-ms-office365-filtering-correlation-id: de0b5f3d-32dc-45b8-b6d7-08deba1ec2ac x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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envelope-from=jamin_lin@aspeedtech.com; helo=TYDPR03CU002.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Prepare the Aspeed SoC model for future platforms that may contain=0A= multiple SRAM regions with different sizes and MMIO mappings.=0A= =0A= The current implementation stores SRAM size information in a single=0A= sram_size field, which limits extensibility when additional SRAM=0A= instances are introduced.=0A= =0A= Convert sram_size into an array-based definition and update all=0A= existing users to reference sram_size[0]. This aligns with the=0A= previous SRAM MemoryRegion array conversion and provides a scalable=0A= foundation for supporting multiple SRAM regions in future SoCs.=0A= =0A= No functional change.=0A= =0A= Signed-off-by: Jamin Lin =0A= ---=0A= include/hw/arm/aspeed_soc.h | 2 +-=0A= hw/arm/aspeed_ast10x0.c | 8 ++++----=0A= hw/arm/aspeed_ast2400.c | 6 +++---=0A= hw/arm/aspeed_ast2600.c | 4 ++--=0A= hw/arm/aspeed_ast27x0.c | 8 ++++----=0A= 5 files changed, 14 insertions(+), 14 deletions(-)=0A= =0A= diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h=0A= index e6942b2936..3a7db959a9 100644=0A= --- a/include/hw/arm/aspeed_soc.h=0A= +++ b/include/hw/arm/aspeed_soc.h=0A= @@ -172,7 +172,7 @@ struct AspeedSoCClass {=0A= /** valid_cpu_types: NULL terminated array of a single CPU type. */=0A= const char * const *valid_cpu_types;=0A= uint32_t silicon_rev;=0A= - uint64_t sram_size;=0A= + uint64_t sram_size[ASPEED_SRAM_NUM];=0A= uint64_t secsram_size;=0A= int pcie_num;=0A= int spis_num;=0A= diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c=0A= index 3e478f7520..9e597a75ec 100644=0A= --- a/hw/arm/aspeed_ast10x0.c=0A= +++ b/hw/arm/aspeed_ast10x0.c=0A= @@ -240,8 +240,8 @@ static bool aspeed_soc_ast10x0_realize(Aspeed10x0SoCSta= te *a, Error **errp)=0A= /* Internal SRAM */=0A= sram_name =3D g_strdup_printf("aspeed.sram.%d",=0A= CPU(a->armv7m.cpu)->cpu_index);=0A= - memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name, sc->sram_siz= e,=0A= - &err);=0A= + memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name,=0A= + sc->sram_size[0], &err);=0A= if (err !=3D NULL) {=0A= error_propagate(errp, err);=0A= return false;=0A= @@ -493,7 +493,7 @@ static void aspeed_soc_ast1030_class_init(ObjectClass *= klass, const void *data)=0A= =0A= sc->valid_cpu_types =3D valid_cpu_types;=0A= sc->silicon_rev =3D AST1030_A1_SILICON_REV;=0A= - sc->sram_size =3D 0xc0000;=0A= + sc->sram_size[0] =3D 0xc0000;=0A= sc->secsram_size =3D 0x40000; /* 256 * KiB */=0A= sc->spis_num =3D 2;=0A= sc->ehcis_num =3D 0;=0A= @@ -521,7 +521,7 @@ static void aspeed_soc_ast1060_class_init(ObjectClass *= klass, const void *data)=0A= =0A= sc->valid_cpu_types =3D valid_cpu_types;=0A= sc->silicon_rev =3D AST1060_A2_SILICON_REV;=0A= - sc->sram_size =3D 0xc0000;=0A= + sc->sram_size[0] =3D 0xc0000;=0A= sc->secsram_size =3D 0x40000; /* 256 * KiB */=0A= sc->spis_num =3D 2;=0A= sc->wdts_num =3D 4;=0A= diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c=0A= index d79aa832f3..c4e5388999 100644=0A= --- a/hw/arm/aspeed_ast2400.c=0A= +++ b/hw/arm/aspeed_ast2400.c=0A= @@ -282,7 +282,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp)=0A= /* SRAM */=0A= sram_name =3D g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_i= ndex);=0A= if (!memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name,=0A= - sc->sram_size, errp)) {=0A= + sc->sram_size[0], errp)) {=0A= return;=0A= }=0A= memory_region_add_subregion(s->memory,=0A= @@ -533,7 +533,7 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *= oc, const void *data)=0A= =0A= sc->valid_cpu_types =3D valid_cpu_types;=0A= sc->silicon_rev =3D AST2400_A1_SILICON_REV;=0A= - sc->sram_size =3D 0x8000;=0A= + sc->sram_size[0] =3D 0x8000;=0A= sc->spis_num =3D 1;=0A= sc->ehcis_num =3D 1;=0A= sc->wdts_num =3D 2;=0A= @@ -560,7 +560,7 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *= oc, const void *data)=0A= =0A= sc->valid_cpu_types =3D valid_cpu_types;=0A= sc->silicon_rev =3D AST2500_A1_SILICON_REV;=0A= - sc->sram_size =3D 0x9000;=0A= + sc->sram_size[0] =3D 0x9000;=0A= sc->spis_num =3D 2;=0A= sc->ehcis_num =3D 2;=0A= sc->wdts_num =3D 3;=0A= diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c=0A= index a69103de89..2f8f49a376 100644=0A= --- a/hw/arm/aspeed_ast2600.c=0A= +++ b/hw/arm/aspeed_ast2600.c=0A= @@ -438,7 +438,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp)=0A= /* SRAM */=0A= sram_name =3D g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_i= ndex);=0A= if (!memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name,=0A= - sc->sram_size, errp)) {=0A= + sc->sram_size[0], errp)) {=0A= return;=0A= }=0A= memory_region_add_subregion(s->memory,=0A= @@ -764,7 +764,7 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *= oc, const void *data)=0A= =0A= sc->valid_cpu_types =3D valid_cpu_types;=0A= sc->silicon_rev =3D AST2600_A3_SILICON_REV;=0A= - sc->sram_size =3D 0x16400;=0A= + sc->sram_size[0] =3D 0x16400;=0A= sc->spis_num =3D 2;=0A= sc->ehcis_num =3D 2;=0A= sc->wdts_num =3D 4;=0A= diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c=0A= index 0fb5e4b24c..30883ea7ce 100644=0A= --- a/hw/arm/aspeed_ast27x0.c=0A= +++ b/hw/arm/aspeed_ast27x0.c=0A= @@ -778,8 +778,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp)=0A= =0A= /* SRAM */=0A= name =3D g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index)= ;=0A= - if (!memory_region_init_ram(&s->sram[0], OBJECT(s), name, sc->sram_siz= e,=0A= - errp)) {=0A= + if (!memory_region_init_ram(&s->sram[0], OBJECT(s), name,=0A= + sc->sram_size[0], errp)) {=0A= return;=0A= }=0A= memory_region_add_subregion(s->memory,=0A= @@ -1151,7 +1151,7 @@ static void aspeed_soc_ast2700a1_class_init(ObjectCla= ss *oc, const void *data)=0A= =0A= sc->valid_cpu_types =3D valid_cpu_types;=0A= sc->silicon_rev =3D AST2700_A1_SILICON_REV;=0A= - sc->sram_size =3D 0x20000;=0A= + sc->sram_size[0] =3D 0x20000;=0A= sc->pcie_num =3D 3;=0A= sc->spis_num =3D 3;=0A= sc->sgpio_num =3D 2;=0A= @@ -1181,7 +1181,7 @@ static void aspeed_soc_ast2700a2_class_init(ObjectCla= ss *oc, const void *data)=0A= =0A= sc->valid_cpu_types =3D valid_cpu_types;=0A= sc->silicon_rev =3D AST2700_A2_SILICON_REV;=0A= - sc->sram_size =3D 0x20000;=0A= + sc->sram_size[0] =3D 0x20000;=0A= sc->pcie_num =3D 3;=0A= sc->spis_num =3D 3;=0A= sc->sgpio_num =3D 2;=0A= -- =0A= 2.43.0=0A=