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Mon, 25 May 2026 05:30:45 +0000 From: Jamin Lin To: =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Kane Chen , Andrew Jeffery , Joel Stanley , Pierrick Bouvier , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: Jamin Lin , Troy Lee Subject: [PATCH v2 6/9] hw/arm/aspeed: Introduce AST1040 A0 SoC model Thread-Topic: [PATCH v2 6/9] hw/arm/aspeed: Introduce AST1040 A0 SoC model Thread-Index: AQHc7AeiOVn0aYf8U0i+aVjJmK/kmA== Date: Mon, 25 May 2026 05:30:45 +0000 Message-ID: <20260525053036.3305181-7-jamin_lin@aspeedtech.com> References: <20260525053036.3305181-1-jamin_lin@aspeedtech.com> In-Reply-To: <20260525053036.3305181-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: TYPPR06MB8206:EE_|TYZPR06MB6657:EE_ x-ms-office365-filtering-correlation-id: 88011879-1172-417c-caf9-08deba1ec57a x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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envelope-from=jamin_lin@aspeedtech.com; helo=SEYPR02CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org The AST1040 is based on an ARM Cortex-M4F CPU core. Since QEMU=0A= currently does not provide Cortex-M4F support, use the existing=0A= Cortex-M4 CPU model as a temporary replacement.=0A= =0A= This initial implementation provides the basic infrastructure=0A= required to boot firmware and run a minimal firmware shell,=0A= including:=0A= =0A= - ARM Cortex-M4 CPU integration=0A= - NVIC interrupt controller support=0A= - Internal HyperRAM and SRAM memory regions=0A= - SCU integration=0A= - UART devices and interrupt wiring=0A= =0A= AST1040 SCU behavior is compatible with the AST2700 SCUIO model,=0A= so reuse the existing AST2700 SCUIO implementation directly=0A= instead of introducing another identical SCU model. This reduces=0A= duplicate code and helps minimize long-term codebase maintenance.=0A= =0A= Several peripherals are currently modeled as unimplemented=0A= devices and can be added incrementally in future updates.=0A= =0A= Signed-off-by: Jamin Lin =0A= ---=0A= hw/arm/aspeed_ast1040.c | 254 ++++++++++++++++++++++++++++++++++++++++=0A= hw/arm/meson.build | 3 +-=0A= 2 files changed, 256 insertions(+), 1 deletion(-)=0A= create mode 100644 hw/arm/aspeed_ast1040.c=0A= =0A= diff --git a/hw/arm/aspeed_ast1040.c b/hw/arm/aspeed_ast1040.c=0A= new file mode 100644=0A= index 0000000000..8efcdad8f6=0A= --- /dev/null=0A= +++ b/hw/arm/aspeed_ast1040.c=0A= @@ -0,0 +1,254 @@=0A= +/*=0A= + * ASPEED AST1040 SoC=0A= + *=0A= + * Copyright (C) 2026 ASPEED Technology Inc.=0A= + *=0A= + * SPDX-License-Identifier: GPL-2.0-or-later=0A= + */=0A= +=0A= +#include "qemu/osdep.h"=0A= +#include "qapi/error.h"=0A= +#include "system/address-spaces.h"=0A= +#include "system/system.h"=0A= +#include "hw/core/qdev-clock.h"=0A= +#include "hw/misc/unimp.h"=0A= +#include "hw/arm/aspeed_soc.h"=0A= +=0A= +static const hwaddr aspeed_soc_ast1040_memmap[] =3D {=0A= + [ASPEED_DEV_SRAM1] =3D 0x00000000, /* Hyper RAM */=0A= + [ASPEED_DEV_FMC] =3D 0x74000000,=0A= + [ASPEED_DEV_SPI0] =3D 0x74010000,=0A= + [ASPEED_DEV_SPI1] =3D 0x74020000,=0A= + [ASPEED_DEV_PWM] =3D 0x740C0000,=0A= + [ASPEED_DEV_UDC] =3D 0x74120000,=0A= + [ASPEED_DEV_SRAM0] =3D 0x74B80000,=0A= + [ASPEED_DEV_ADC] =3D 0x74C00000,=0A= + [ASPEED_DEV_JTAG0] =3D 0x74C01000,=0A= + [ASPEED_DEV_SCU] =3D 0x74C02000,=0A= + [ASPEED_DEV_ESPI] =3D 0x74C05000,=0A= + [ASPEED_DEV_JTAG1] =3D 0x74C09000,=0A= + [ASPEED_DEV_GPIO] =3D 0x74C0B000,=0A= + [ASPEED_DEV_SGPIOM0] =3D 0x74C0C000,=0A= + [ASPEED_DEV_SGPIOM1] =3D 0x74C0D000,=0A= + [ASPEED_DEV_I2C] =3D 0x74C0F000,=0A= + [ASPEED_DEV_I3C] =3D 0x74C20000,=0A= + [ASPEED_DEV_UART0] =3D 0x74C33000,=0A= + [ASPEED_DEV_UART1] =3D 0x74C33100,=0A= + [ASPEED_DEV_UART2] =3D 0x74C33200,=0A= + [ASPEED_DEV_UART3] =3D 0x74C33300,=0A= + [ASPEED_DEV_UART4] =3D 0x74C33400,=0A= + [ASPEED_DEV_UART5] =3D 0x74C33500,=0A= + [ASPEED_DEV_UART6] =3D 0x74C33600,=0A= + [ASPEED_DEV_UART7] =3D 0x74C33700,=0A= + [ASPEED_DEV_UART8] =3D 0x74C33800,=0A= + [ASPEED_DEV_UART9] =3D 0x74C33900,=0A= + [ASPEED_DEV_UART10] =3D 0x74C33A00,=0A= + [ASPEED_DEV_UART11] =3D 0x74C33B00,=0A= + [ASPEED_DEV_UART12] =3D 0x74C33C00,=0A= + [ASPEED_DEV_WDT] =3D 0x74C37000,=0A= + [ASPEED_DEV_TIMER1] =3D 0x74C3A000,=0A= +};=0A= +=0A= +static const int aspeed_soc_ast1040_irqmap[] =3D {=0A= + [ASPEED_DEV_ESPI] =3D 10,=0A= + [ASPEED_DEV_I2C] =3D 64, /* 64 ~ 77 */=0A= + [ASPEED_DEV_ADC] =3D 80,=0A= + [ASPEED_DEV_GPIO] =3D 82,=0A= + [ASPEED_DEV_SGPIOM0] =3D 85,=0A= + [ASPEED_DEV_TIMER1] =3D 92,=0A= + [ASPEED_DEV_I3C] =3D 96, /* 96 ~ 103 */=0A= + [ASPEED_DEV_WDT] =3D 112,=0A= + [ASPEED_DEV_FMC] =3D 121,=0A= + [ASPEED_DEV_SPI0] =3D 122,=0A= + [ASPEED_DEV_SPI1] =3D 123,=0A= + [ASPEED_DEV_PWM] =3D 125,=0A= + [ASPEED_DEV_UART0] =3D 135,=0A= + [ASPEED_DEV_UART1] =3D 136,=0A= + [ASPEED_DEV_UART2] =3D 137,=0A= + [ASPEED_DEV_UART3] =3D 138,=0A= + [ASPEED_DEV_UART4] =3D 139,=0A= + [ASPEED_DEV_UART5] =3D 140,=0A= + [ASPEED_DEV_UART6] =3D 141,=0A= + [ASPEED_DEV_UART7] =3D 142,=0A= + [ASPEED_DEV_UART8] =3D 143,=0A= + [ASPEED_DEV_UART9] =3D 144,=0A= + [ASPEED_DEV_UART10] =3D 145,=0A= + [ASPEED_DEV_UART11] =3D 146,=0A= + [ASPEED_DEV_UART12] =3D 147,=0A= + [ASPEED_DEV_JTAG0] =3D 162,=0A= +};=0A= +=0A= +static qemu_irq aspeed_soc_ast1040_get_irq(AspeedSoCState *s, int dev)=0A= +{=0A= + Aspeed10x0SoCState *a =3D ASPEED10X0_SOC(s);=0A= + AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s);=0A= +=0A= + return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]);=0A= +}=0A= +=0A= +static void aspeed_soc_ast1040_init(Object *obj)=0A= +{=0A= + Aspeed10x0SoCState *a =3D ASPEED10X0_SOC(obj);=0A= + AspeedSoCState *s =3D ASPEED_SOC(obj);=0A= + AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s);=0A= + int i;=0A= + object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);=0A= +=0A= + s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);= =0A= +=0A= + /* AST1040 uses the AST2700 SCUIO model */=0A= + object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCUIO);= =0A= + qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);= =0A= +=0A= + object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), "hw-strap= 1");=0A= + object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), "hw-strap= 2");=0A= +=0A= + for (i =3D 0; i < sc->uarts_num; i++) {=0A= + object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_M= M);=0A= + }=0A= +=0A= + object_initialize_child(obj, "pwm", &s->pwm, TYPE_UNIMPLEMENTED_DEVICE= );=0A= + object_initialize_child(obj, "espi", &s->espi, TYPE_UNIMPLEMENTED_DEVI= CE);=0A= + object_initialize_child(obj, "udc", &s->udc, TYPE_UNIMPLEMENTED_DEVICE= );=0A= + object_initialize_child(obj, "sgpiom[0]", &s->sgpiom[0],=0A= + TYPE_UNIMPLEMENTED_DEVICE);=0A= + object_initialize_child(obj, "sgpiom[1]", &s->sgpiom[1],=0A= + TYPE_UNIMPLEMENTED_DEVICE);=0A= + object_initialize_child(obj, "jtag[0]", &s->jtag[0],=0A= + TYPE_UNIMPLEMENTED_DEVICE);=0A= + object_initialize_child(obj, "jtag[1]", &s->jtag[1],=0A= + TYPE_UNIMPLEMENTED_DEVICE);=0A= +}=0A= +=0A= +static void aspeed_soc_ast1040_realize(DeviceState *dev_soc, Error **errp)= =0A= +{=0A= + Aspeed10x0SoCState *a =3D ASPEED10X0_SOC(dev_soc);=0A= + AspeedSoCState *s =3D ASPEED_SOC(dev_soc);=0A= + AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s);=0A= + g_autofree char *hyperram_name =3D NULL;=0A= + g_autofree char *sram_name =3D NULL;=0A= + DeviceState *armv7m;=0A= + Error *err =3D NULL;=0A= + int uart;=0A= + int i;=0A= +=0A= + if (!clock_has_source(s->sysclk)) {=0A= + error_setg(errp, "sysclk clock must be wired up by the board code"= );=0A= + return;=0A= + }=0A= +=0A= + /* AST1040 CPU Core */=0A= + armv7m =3D DEVICE(&a->armv7m);=0A= + qdev_prop_set_uint32(armv7m, "num-irq", 256);=0A= + qdev_prop_set_string(armv7m, "cpu-type",=0A= + aspeed_soc_cpu_type(sc->valid_cpu_types));=0A= + qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);=0A= + object_property_set_link(OBJECT(&a->armv7m), "memory",=0A= + OBJECT(s->memory), &error_abort);=0A= + sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);=0A= +=0A= + /* Internal SRAM */=0A= + sram_name =3D g_strdup_printf("aspeed.sram.%d",=0A= + CPU(a->armv7m.cpu)->cpu_index);=0A= + memory_region_init_ram(&s->sram[0], OBJECT(s), sram_name,=0A= + sc->sram_size[0], &err);=0A= + if (err) {=0A= + error_propagate(errp, err);=0A= + return;=0A= + }=0A= + memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM0],= =0A= + &s->sram[0]);=0A= +=0A= + /* Internal Hyper RAM */=0A= + hyperram_name =3D g_strdup_printf("aspeed.hyperram.%d",=0A= + CPU(a->armv7m.cpu)->cpu_index);=0A= + memory_region_init_ram(&s->sram[1], OBJECT(s), hyperram_name,=0A= + sc->sram_size[1], &err);=0A= + if (err) {=0A= + error_propagate(errp, err);=0A= + return;=0A= + }=0A= + memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM1],= =0A= + &s->sram[1]);=0A= +=0A= + /* SCU */=0A= + if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {=0A= + return;=0A= + }=0A= + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0,=0A= + sc->memmap[ASPEED_DEV_SCU]);=0A= +=0A= + /* UART */=0A= + for (i =3D 0, uart =3D sc->uarts_base; i < sc->uarts_num; i++, uart++)= {=0A= + if (!aspeed_soc_uart_realize(s->memory, &s->uart[i],=0A= + sc->memmap[uart], errp)) {=0A= + return;=0A= + }=0A= + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,=0A= + aspeed_soc_ast1040_get_irq(s, uart));=0A= + }=0A= +=0A= + /* Unimplemented peripherals */=0A= + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->pwm),=0A= + "aspeed.pwm",=0A= + sc->memmap[ASPEED_DEV_PWM], 0x10000);=0A= +=0A= + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->espi),=0A= + "aspeed.espi",=0A= + sc->memmap[ASPEED_DEV_ESPI], 0x1000);=0A= +=0A= + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->udc),=0A= + "aspeed.udc",=0A= + sc->memmap[ASPEED_DEV_UDC], 0x4000);=0A= +=0A= + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->sgpiom[0])= ,=0A= + "aspeed.sgpiom0",=0A= + sc->memmap[ASPEED_DEV_SGPIOM0], 0x1000);= =0A= +=0A= + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->sgpiom[1])= ,=0A= + "aspeed.sgpiom1",=0A= + sc->memmap[ASPEED_DEV_SGPIOM1], 0x1000);= =0A= +=0A= + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->jtag[0]),= =0A= + "aspeed.jtag0",=0A= + sc->memmap[ASPEED_DEV_JTAG0], 0x100);=0A= +=0A= + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->jtag[1]),= =0A= + "aspeed.jtag1",=0A= + sc->memmap[ASPEED_DEV_JTAG1], 0x100);=0A= +}=0A= +=0A= +static void aspeed_soc_ast1040_class_init(ObjectClass *klass, const void *= data)=0A= +{=0A= + static const char * const valid_cpu_types[] =3D {=0A= + ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */=0A= + NULL=0A= + };=0A= + DeviceClass *dc =3D DEVICE_CLASS(klass);=0A= + AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(dc);=0A= +=0A= + /* Reason: The Aspeed SoC can only be instantiated from a board */=0A= + dc->user_creatable =3D false;=0A= + dc->realize =3D aspeed_soc_ast1040_realize;=0A= +=0A= + sc->valid_cpu_types =3D valid_cpu_types;=0A= + sc->silicon_rev =3D AST1040_A0_SILICON_REV;=0A= + sc->sram_size[0] =3D 128 * KiB;=0A= + sc->sram_size[1] =3D 16 * MiB; /* Hyper RAM */=0A= + sc->uarts_num =3D 13;=0A= + sc->uarts_base =3D ASPEED_DEV_UART0;=0A= + sc->irqmap =3D aspeed_soc_ast1040_irqmap;=0A= + sc->memmap =3D aspeed_soc_ast1040_memmap;=0A= + sc->num_cpus =3D 1;=0A= +}=0A= +=0A= +static const TypeInfo aspeed_soc_ast1040_types[] =3D {=0A= + {=0A= + .name =3D "ast1040-a0",=0A= + .parent =3D TYPE_ASPEED10X0_SOC,=0A= + .instance_init =3D aspeed_soc_ast1040_init,=0A= + .class_init =3D aspeed_soc_ast1040_class_init,=0A= + }=0A= +};=0A= +=0A= +DEFINE_TYPES(aspeed_soc_ast1040_types)=0A= diff --git a/hw/arm/meson.build b/hw/arm/meson.build=0A= index 80068f70bb..fa3a848492 100644=0A= --- a/hw/arm/meson.build=0A= +++ b/hw/arm/meson.build=0A= @@ -62,7 +62,8 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(=0A= 'aspeed_ast2600_gb200nvl.c',=0A= 'aspeed_ast2600_rainier.c',=0A= 'aspeed_ast10x0.c',=0A= - 'aspeed_ast10x0_evb.c'))=0A= + 'aspeed_ast10x0_evb.c',=0A= + 'aspeed_ast1040.c'))=0A= arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: = files(=0A= 'aspeed_ast1700.c',=0A= 'aspeed_ast27x0.c',=0A= -- =0A= 2.43.0=0A=