From: Francesco Dolcini <francesco@dolcini.it>
To: Simona Toaca <simona.toaca@oss.nxp.com>
Cc: Emanuele Ghidoli <ghidoliemanuele@gmail.com>,
uboot-imx@nxp.com, u-boot@lists.denx.de,
Stefano Babic <sbabic@nabladev.com>,
festevam@gmail.com, peng.fan@nxp.com, alice.guo@nxp.com,
ye.li@nxp.com, simona.toaca@nxp.com, viorel.suman@nxp.com,
fedor.ross@ifm.com, marex@nabladev.com,
joao.goncalves@toradex.com, ravi@prevas.dk, ping.bai@nxp.com,
ji.luo@nxp.com, qijian.guo@nxp.com
Subject: Re: [PATCH v4 1/4] imx9: Add support for saving DDR training data to NVM
Date: Thu, 28 May 2026 09:37:34 +0200 [thread overview]
Message-ID: <20260528073734.GA17049@francesco-nb> (raw)
In-Reply-To: <nesqj4lgl65zv6ugh5fcott4ticwzdvur2drwyppkutvbtbyof@gq23nkzbmo24>
On Wed, May 27, 2026 at 05:33:36PM +0300, Simona Toaca wrote:
> On Mon, May 25, 2026 at 10:59:00AM +0200, Emanuele Ghidoli wrote:
> >
> >
> > On 4/30/26 10:33, Simona Toaca (OSS) wrote:
> > > From: Simona Toaca <simona.toaca@nxp.com>
> > >
> > > +/**
> > > + * This structure needs to be aligned with the one in OEI.
> > > + */
> > > +struct ddrphy_qb_state {
> > > + u32 crc; /* Used for ensuring integrity in DRAM */
> > > +#define MAC_LENGTH 8 /* 256 bits, 32-bit aligned */
> > > + u32 mac[MAC_LENGTH]; /* For 95A0/1 use mac[0] to keep CRC32 value */
> > > + u8 trained_vrefca_a0;
> > > + u8 trained_vrefca_a1;
> [...]
>
> > > + u16 acsm[DDRPHY_QB_ACSM_SIZE];
> > > + u16 pst[DDRPHY_QB_PST_SIZE];
> > > +};
> >
> > Hi Simona,
> >
> > Would you consider reserving a small u16 board-defined field at the
> > end of struct ddrphy_qb_state? Something like:
> >
> > u16 board_ddr_config; /* board-defined tag, opaque to U-Boot */
> >
> > Use case: boards that carry multiple LPDDR configurations
> > (single-/dual-rank, different sizes, ...). At QuickBoot time the
> > boot code needs to know which configuration produced the persisted
> > PHY training data, in order to load the matching timing table
> > before DDRC init, in OEI. A 16-bit board-defined identifier is enough; the
> > value is opaque to U-Boot.
> >
> I am taking into consideration adding such a field into qb_state
> in the future, but for now we do not support a mechanism
> for deciding the dram timing at runtime.
The reality is that we are forking your OEI (AFAIK you do not take
patches) to support our boards and our use case. So we (Toradex) have it
already, and it is working 100% fine.
What is tricky here is that this structure is an ABI / contract between
the OEI firmware and U-Boot.
Just to anticipate your potential answer, our boards just work with
mainline U-Boot, so asking us to have a patch and fork U-Boot is not an
option.
Francesco
next prev parent reply other threads:[~2026-05-28 7:37 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-30 8:33 [PATCH v4 0/4] imx9{4,5,52}: Add Quickboot support Simona Toaca (OSS)
2026-04-30 8:33 ` [PATCH v4 1/4] imx9: Add support for saving DDR training data to NVM Simona Toaca (OSS)
2026-05-25 8:59 ` Emanuele Ghidoli
2026-05-27 14:33 ` Simona Toaca
2026-05-28 7:37 ` Francesco Dolcini [this message]
2026-05-28 5:25 ` Kumar, Udit
2026-06-02 10:59 ` Simona Toaca
2026-06-03 7:24 ` Francesco Dolcini
2026-06-03 8:13 ` Kumar, Udit
2026-06-02 11:20 ` Marek Vasut
2026-06-02 13:46 ` Simona Toaca
2026-06-02 14:11 ` Marek Vasut
2026-06-03 4:57 ` Marek Vasut
2026-06-03 13:31 ` Simona Toaca
2026-06-03 13:53 ` Marek Vasut
2026-06-04 12:04 ` Simona Toaca
2026-04-30 8:33 ` [PATCH v4 2/4] arm: mach-imx: Add command to expose QB functionality Simona Toaca (OSS)
2026-04-30 8:33 ` [PATCH v4 3/4] board: nxp: imx9{4, 5, 52}_evk: Add qb save option in SPL Simona Toaca (OSS)
2026-04-30 8:33 ` [PATCH v4 4/4] doc: board: nxp: Add Quickboot documentation Simona Toaca (OSS)
2026-05-28 5:23 ` [PATCH v4 0/4] imx9{4,5,52}: Add Quickboot support Kumar, Udit
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