Re: [PATCH v3 0/9] s390: Improve this_cpu operations

[David Laight <david.laight.linux@gmail.com>]

On Wed, 27 May 2026 13:38:06 -0700
Yang Shi <yang@os.amperecomputing.com> wrote:

> On 5/27/26 12:09 PM, Christoph Lameter (Ampere) wrote:
> > On Fri, 22 May 2026, Heiko Carstens wrote:
> >  
> >> Also with the current proposal I only did some quick micro benchmarks,
> >> which resulted in 0-1% improvement, which is in the expected range.
> >>
> >> It is amazing to see the performance improvements you see on arm64, however
> >> I believe that is mainly because of the large amount of code which is
> >> generated by the arm64 implementations of the preempt primitives
> >> __preempt_count_add() and __preempt_count_dec_and_test().  
> > The code is generated if you have no arch specific per cpu mechanism and
> > preemption must be supported. We have now the situation that we cannot
> > switch off preemption support anymore.
> >
> > It seem that S390 has this mechanism in a small way and therefore can
> > avoid the preempt enable/disable.
> >
> > It is not the quantity of code here. The preempt enable/disable can only
> > be avoided if there is a single instruction doing the per cpu operation. A
> > single instruction cannot be interupted and therefore is preemption safe.
> >
> >  
> >> That's a big difference to s390: for both primitives the result is a single
> >> instruction.  
> > Ok then you can already use single instructions like x86 and will not have
> > preempt enable/disable overhead.  
> 
> I don't think S390 can do it in one single instruction. IIUC, Heiko 
> means preempt_enable/disable is a single instruction on s390, but it is 
> RMW on ARM64 (3 instructions for each).

The proposed 'trick' for s390 is a sort of a temporary global register
that accesses the per-cpu data.
s390 seems to have it relatively easy because of the 8k of per-cpu data
and the atomic add/and/or with memory.
x86 has two global registers (%fs and %gs) as well as atomic add.

But AFAICT arm64 (and probably others) has nothing that helps.
Allocating a global register for the per-cpu data has been suggested.
Using the mmu to generate a page of cpu-private data would make
the preempt primitives much cheaper without the difficulties of
having two addresses for per-cpu data and any related cache issues.

> 
> Thanks,
> Yang
> 
> >
> > I am not sure what David Laight's code is supposed to do. Seems weird to
> > me.

I've forgotten what I suggested, was probably broken...

-- David

> >  
>