From: Ian Rogers <irogers@google.com>
To: "Peter Zijlstra" <peterz@infradead.org>,
"Ingo Molnar" <mingo@redhat.com>,
"Arnaldo Carvalho de Melo" <acme@kernel.org>,
"Namhyung Kim" <namhyung@kernel.org>,
"Alexander Shishkin" <alexander.shishkin@linux.intel.com>,
"Jiri Olsa" <jolsa@kernel.org>,
"Adrian Hunter" <adrian.hunter@intel.com>,
"James Clark" <james.clark@linaro.org>,
"Andreas Färber" <afaerber@suse.de>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Dapeng Mi" <dapeng1.mi@linux.intel.com>,
"Thomas Falcon" <thomas.falcon@intel.com>,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org
Cc: Ian Rogers <irogers@google.com>
Subject: [PATCH v1 06/12] perf vendor events intel: Update grandridge events from 1.11 to 1.12
Date: Thu, 28 May 2026 21:51:48 -0700 [thread overview]
Message-ID: <20260529045155.311805-7-irogers@google.com> (raw)
In-Reply-To: <20260529045155.311805-1-irogers@google.com>
The updated events and metrics were published in:
https://github.com/intel/perfmon/commit/50159a77124571c633adc2625fa7b566010d5001
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/grandridge/cache.json | 56 ++++++++++++++++
.../arch/x86/grandridge/floating-point.json | 8 +++
.../arch/x86/grandridge/frontend.json | 64 +++++++++++++++++++
.../arch/x86/grandridge/pipeline.json | 15 +++++
.../arch/x86/grandridge/uncore-io.json | 15 ++---
.../arch/x86/grandridge/uncore-memory.json | 32 +++++-----
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
7 files changed, 167 insertions(+), 25 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/grandridge/cache.json b/tools/perf/pmu-events/arch/x86/grandridge/cache.json
index 0aa921ba89b4..393ce9421c12 100644
--- a/tools/perf/pmu-events/arch/x86/grandridge/cache.json
+++ b/tools/perf/pmu-events/arch/x86/grandridge/cache.json
@@ -121,6 +121,14 @@
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
+ {
+ "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which missed in the L2 cache.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x35",
+ "EventName": "MEM_BOUND_STALLS_IFETCH.L2_MISS",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x7e"
+ },
{
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an ICACHE or ITLB miss which hit in the LLC. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -129,6 +137,14 @@
"SampleAfterValue": "1000003",
"UMask": "0x6"
},
+ {
+ "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an ICACHE or ITLB miss which hit in the LLC, no snoop was required. LLC provides the data. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x35",
+ "EventName": "MEM_BOUND_STALLS_IFETCH.LLC_HIT_NOSNOOP",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x2"
+ },
{
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an ICACHE or ITLB miss which missed all the caches. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -137,6 +153,14 @@
"SampleAfterValue": "1000003",
"UMask": "0x78"
},
+ {
+ "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an ICACHE or ITLB miss which missed all the caches. DRAM, MMIO or other LOCAL memory type provides the data. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x35",
+ "EventName": "MEM_BOUND_STALLS_IFETCH.LLC_MISS_LOCALMEM",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x50"
+ },
{
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an L1 demand load miss.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -154,6 +178,14 @@
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
+ {
+ "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which missed in the L2 cache.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x34",
+ "EventName": "MEM_BOUND_STALLS_LOAD.L2_MISS",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x7e"
+ },
{
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -162,6 +194,14 @@
"SampleAfterValue": "1000003",
"UMask": "0x6"
},
+ {
+ "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC, a snoop was required, the snoop misses or the snoop hits but NO_FWD. LLC provides the data. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x34",
+ "EventName": "MEM_BOUND_STALLS_LOAD.LLC_HIT_SNOOP",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x4"
+ },
{
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the local caches. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -170,6 +210,14 @@
"SampleAfterValue": "1000003",
"UMask": "0x78"
},
+ {
+ "BriefDescription": "Counts the number of unhalted cycles when the core is stalled to a demand load miss and the data was provided from an unknown source. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x34",
+ "EventName": "MEM_BOUND_STALLS_LOAD.LLC_MISS_LOCALMEM",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x50"
+ },
{
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled to a store buffer full condition",
"Counter": "0,1,2,3,4,5,6,7",
@@ -178,6 +226,14 @@
"SampleAfterValue": "1000003",
"UMask": "0x80"
},
+ {
+ "BriefDescription": "Counts the total number of load ops retired that miss the L3 cache.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xd3",
+ "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.ALL",
+ "SampleAfterValue": "1000003",
+ "UMask": "0xff"
+ },
{
"BriefDescription": "Counts the number of load ops retired that miss the L3 cache and hit in DRAM",
"Counter": "0,1,2,3,4,5,6,7",
diff --git a/tools/perf/pmu-events/arch/x86/grandridge/floating-point.json b/tools/perf/pmu-events/arch/x86/grandridge/floating-point.json
index 5266eed969be..c567f073713c 100644
--- a/tools/perf/pmu-events/arch/x86/grandridge/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/grandridge/floating-point.json
@@ -90,6 +90,14 @@
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
+ {
+ "BriefDescription": "Counts the number of uops executed on floating point and vector integer store data port.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xb2",
+ "EventName": "FP_VINT_UOPS_EXECUTED.STD",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x1"
+ },
{
"BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",
"Counter": "0,1,2,3,4,5,6,7",
diff --git a/tools/perf/pmu-events/arch/x86/grandridge/frontend.json b/tools/perf/pmu-events/arch/x86/grandridge/frontend.json
index fef5cba533bb..8a591e31d331 100644
--- a/tools/perf/pmu-events/arch/x86/grandridge/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/grandridge/frontend.json
@@ -8,6 +8,54 @@
"SampleAfterValue": "200003",
"UMask": "0x1"
},
+ {
+ "BriefDescription": "Counts the number of instructions retired that were tagged with having preceded with frontend bound behavior",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xc6",
+ "EventName": "FRONTEND_RETIRED.ALL",
+ "SampleAfterValue": "1000003"
+ },
+ {
+ "BriefDescription": "Counts the number of instruction retired that are tagged after a branch instruction causes bubbles/empty issue slots due to a baclear",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xc6",
+ "EventName": "FRONTEND_RETIRED.BRANCH_DETECT",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "Counts the number of instruction retired that are tagged after a branch instruction causes bubbles /empty issue slots due to a btclear",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xc6",
+ "EventName": "FRONTEND_RETIRED.BRANCH_RESTEER",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x40"
+ },
+ {
+ "BriefDescription": "Counts the number of instructions retired that were tagged following an ms flow due to the bubble/wasted issue slot from exiting long ms flow",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xc6",
+ "EventName": "FRONTEND_RETIRED.CISC",
+ "PublicDescription": "Counts the number of instructions retired that were tagged following an ms flow due to the bubble/wasted issue slot from exiting long ms flow",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts the number of instructions retired that were tagged every cycle the decoder is unable to send 3 uops per cycle.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xc6",
+ "EventName": "FRONTEND_RETIRED.DECODE",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x8"
+ },
+ {
+ "BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to icache miss",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xc6",
+ "EventName": "FRONTEND_RETIRED.ICACHE",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x20"
+ },
{
"BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss",
"Counter": "0,1,2,3,4,5,6,7",
@@ -16,6 +64,22 @@
"SampleAfterValue": "1000003",
"UMask": "0x10"
},
+ {
+ "BriefDescription": "Counts the number of instruction retired tagged after a wasted issue slot if none of the previous events occurred",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xc6",
+ "EventName": "FRONTEND_RETIRED.OTHER",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x80"
+ },
+ {
+ "BriefDescription": "Counts the number of instruction retired that are tagged after a branch instruction causes bubbles/empty issue slots due to a predecode wrong.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xc6",
+ "EventName": "FRONTEND_RETIRED.PREDECODE",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x4"
+ },
{
"BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.",
"Counter": "0,1,2,3,4,5,6,7",
diff --git a/tools/perf/pmu-events/arch/x86/grandridge/pipeline.json b/tools/perf/pmu-events/arch/x86/grandridge/pipeline.json
index 20986b987e18..0a8f7d327150 100644
--- a/tools/perf/pmu-events/arch/x86/grandridge/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/grandridge/pipeline.json
@@ -260,6 +260,13 @@
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
+ {
+ "BriefDescription": "Counts the total number of machine clears for any reason including, but not limited to, memory ordering, memory disambiguation, SMC, and FP assist.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xc3",
+ "EventName": "MACHINE_CLEARS.ANY",
+ "SampleAfterValue": "20003"
+ },
{
"BriefDescription": "Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -268,6 +275,14 @@
"SampleAfterValue": "20003",
"UMask": "0x8"
},
+ {
+ "BriefDescription": "Counts the number of machines clears due to memory renaming.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xc3",
+ "EventName": "MACHINE_CLEARS.MRN_NUKE",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x80"
+ },
{
"BriefDescription": "Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs.",
"Counter": "0,1,2,3,4,5,6,7",
diff --git a/tools/perf/pmu-events/arch/x86/grandridge/uncore-io.json b/tools/perf/pmu-events/arch/x86/grandridge/uncore-io.json
index 764cf2f0b4a8..1a495a89ed57 100644
--- a/tools/perf/pmu-events/arch/x86/grandridge/uncore-io.json
+++ b/tools/perf/pmu-events/arch/x86/grandridge/uncore-io.json
@@ -824,7 +824,7 @@
"Unit": "IIO"
},
{
- "BriefDescription": "-",
+ "BriefDescription": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT",
"Counter": "0,1,2,3",
"EventCode": "0x8e",
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT",
@@ -836,7 +836,7 @@
"Unit": "IIO"
},
{
- "BriefDescription": "-",
+ "BriefDescription": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P",
"Counter": "0,1,2,3",
"EventCode": "0x8e",
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P",
@@ -848,7 +848,7 @@
"Unit": "IIO"
},
{
- "BriefDescription": "-",
+ "BriefDescription": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P",
"Counter": "0,1,2,3",
"EventCode": "0x8e",
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P",
@@ -860,7 +860,7 @@
"Unit": "IIO"
},
{
- "BriefDescription": "-",
+ "BriefDescription": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST",
"Counter": "0,1,2,3",
"EventCode": "0x8e",
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST",
@@ -872,7 +872,7 @@
"Unit": "IIO"
},
{
- "BriefDescription": "-",
+ "BriefDescription": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM",
"Counter": "0,1,2,3",
"EventCode": "0x8e",
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM",
@@ -884,7 +884,7 @@
"Unit": "IIO"
},
{
- "BriefDescription": "-",
+ "BriefDescription": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB",
"Counter": "0,1,2,3",
"EventCode": "0x8e",
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB",
@@ -896,7 +896,7 @@
"Unit": "IIO"
},
{
- "BriefDescription": "-",
+ "BriefDescription": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX",
"Counter": "0,1,2,3",
"EventCode": "0x8e",
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX",
@@ -915,7 +915,6 @@
"FCMask": "0x01",
"PerPkg": "1",
"PortMask": "0x0FF",
- "PublicDescription": "-",
"UMask": "0x4",
"Unit": "IIO"
},
diff --git a/tools/perf/pmu-events/arch/x86/grandridge/uncore-memory.json b/tools/perf/pmu-events/arch/x86/grandridge/uncore-memory.json
index 6a11e5505957..8413391d752c 100644
--- a/tools/perf/pmu-events/arch/x86/grandridge/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/grandridge/uncore-memory.json
@@ -195,7 +195,7 @@
"EventName": "UNC_M_MR4_2XREF_CYCLES.SCH0_DIMM0",
"Experimental": "1",
"PerPkg": "1",
- "PublicDescription": "-",
+ "PublicDescription": "UNC_M_MR4_2XREF_CYCLES.SCH0_DIMM0",
"UMask": "0x1",
"Unit": "IMC"
},
@@ -206,7 +206,7 @@
"EventName": "UNC_M_MR4_2XREF_CYCLES.SCH0_DIMM1",
"Experimental": "1",
"PerPkg": "1",
- "PublicDescription": "-",
+ "PublicDescription": "UNC_M_MR4_2XREF_CYCLES.SCH0_DIMM1",
"UMask": "0x2",
"Unit": "IMC"
},
@@ -217,7 +217,7 @@
"EventName": "UNC_M_MR4_2XREF_CYCLES.SCH1_DIMM0",
"Experimental": "1",
"PerPkg": "1",
- "PublicDescription": "-",
+ "PublicDescription": "UNC_M_MR4_2XREF_CYCLES.SCH1_DIMM0",
"UMask": "0x4",
"Unit": "IMC"
},
@@ -228,7 +228,7 @@
"EventName": "UNC_M_MR4_2XREF_CYCLES.SCH1_DIMM1",
"Experimental": "1",
"PerPkg": "1",
- "PublicDescription": "-",
+ "PublicDescription": "UNC_M_MR4_2XREF_CYCLES.SCH1_DIMM1",
"UMask": "0x8",
"Unit": "IMC"
},
@@ -239,7 +239,7 @@
"EventName": "UNC_M_PDC_MR4ACTIVE_CYCLES.SCH0_DIMM0",
"Experimental": "1",
"PerPkg": "1",
- "PublicDescription": "-",
+ "PublicDescription": "UNC_M_PDC_MR4ACTIVE_CYCLES.SCH0_DIMM0",
"UMask": "0x1",
"Unit": "IMC"
},
@@ -250,7 +250,7 @@
"EventName": "UNC_M_PDC_MR4ACTIVE_CYCLES.SCH0_DIMM1",
"Experimental": "1",
"PerPkg": "1",
- "PublicDescription": "-",
+ "PublicDescription": "UNC_M_PDC_MR4ACTIVE_CYCLES.SCH0_DIMM1",
"UMask": "0x2",
"Unit": "IMC"
},
@@ -261,7 +261,7 @@
"EventName": "UNC_M_PDC_MR4ACTIVE_CYCLES.SCH1_DIMM0",
"Experimental": "1",
"PerPkg": "1",
- "PublicDescription": "-",
+ "PublicDescription": "UNC_M_PDC_MR4ACTIVE_CYCLES.SCH1_DIMM0",
"UMask": "0x4",
"Unit": "IMC"
},
@@ -272,7 +272,7 @@
"EventName": "UNC_M_PDC_MR4ACTIVE_CYCLES.SCH1_DIMM1",
"Experimental": "1",
"PerPkg": "1",
- "PublicDescription": "-",
+ "PublicDescription": "UNC_M_PDC_MR4ACTIVE_CYCLES.SCH1_DIMM1",
"UMask": "0x8",
"Unit": "IMC"
},
@@ -617,7 +617,7 @@
"EventName": "UNC_M_THROTTLE_CRIT_CYCLES.SLOT0",
"Experimental": "1",
"PerPkg": "1",
- "PublicDescription": "-",
+ "PublicDescription": "UNC_M_THROTTLE_CRIT_CYCLES.SLOT0",
"UMask": "0x1",
"Unit": "IMC"
},
@@ -628,7 +628,7 @@
"EventName": "UNC_M_THROTTLE_CRIT_CYCLES.SLOT1",
"Experimental": "1",
"PerPkg": "1",
- "PublicDescription": "-",
+ "PublicDescription": "UNC_M_THROTTLE_CRIT_CYCLES.SLOT1",
"UMask": "0x2",
"Unit": "IMC"
},
@@ -639,7 +639,7 @@
"EventName": "UNC_M_THROTTLE_HIGH_CYCLES.SLOT0",
"Experimental": "1",
"PerPkg": "1",
- "PublicDescription": "-",
+ "PublicDescription": "UNC_M_THROTTLE_HIGH_CYCLES.SLOT0",
"UMask": "0x1",
"Unit": "IMC"
},
@@ -650,7 +650,7 @@
"EventName": "UNC_M_THROTTLE_HIGH_CYCLES.SLOT1",
"Experimental": "1",
"PerPkg": "1",
- "PublicDescription": "-",
+ "PublicDescription": "UNC_M_THROTTLE_HIGH_CYCLES.SLOT1",
"UMask": "0x2",
"Unit": "IMC"
},
@@ -661,7 +661,7 @@
"EventName": "UNC_M_THROTTLE_LOW_CYCLES.SLOT0",
"Experimental": "1",
"PerPkg": "1",
- "PublicDescription": "-",
+ "PublicDescription": "UNC_M_THROTTLE_LOW_CYCLES.SLOT0",
"UMask": "0x1",
"Unit": "IMC"
},
@@ -672,7 +672,7 @@
"EventName": "UNC_M_THROTTLE_LOW_CYCLES.SLOT1",
"Experimental": "1",
"PerPkg": "1",
- "PublicDescription": "-",
+ "PublicDescription": "UNC_M_THROTTLE_LOW_CYCLES.SLOT1",
"UMask": "0x2",
"Unit": "IMC"
},
@@ -683,7 +683,7 @@
"EventName": "UNC_M_THROTTLE_MID_CYCLES.SLOT0",
"Experimental": "1",
"PerPkg": "1",
- "PublicDescription": "-",
+ "PublicDescription": "UNC_M_THROTTLE_MID_CYCLES.SLOT0",
"UMask": "0x1",
"Unit": "IMC"
},
@@ -694,7 +694,7 @@
"EventName": "UNC_M_THROTTLE_MID_CYCLES.SLOT1",
"Experimental": "1",
"PerPkg": "1",
- "PublicDescription": "-",
+ "PublicDescription": "UNC_M_THROTTLE_MID_CYCLES.SLOT1",
"UMask": "0x2",
"Unit": "IMC"
},
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index b6d4d37bcf99..a1548f1306a6 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -12,7 +12,7 @@ GenuineIntel-6-9[6C],v1.05,elkhartlake,core
GenuineIntel-6-CF,v1.23,emeraldrapids,core
GenuineIntel-6-5[CF],v13,goldmont,core
GenuineIntel-6-7A,v1.01,goldmontplus,core
-GenuineIntel-6-B6,v1.11,grandridge,core
+GenuineIntel-6-B6,v1.12,grandridge,core
GenuineIntel-6-A[DE],v1.17,graniterapids,core
GenuineIntel-6-(3C|45|46),v36,haswell,core
GenuineIntel-6-3F,v29,haswellx,core
--
2.54.0.823.g6e5bcc1fc9-goog
next prev parent reply other threads:[~2026-05-29 4:52 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-29 4:51 [PATCH v1 00/12] perf vendor events intel: update Ian Rogers
2026-05-29 4:51 ` [PATCH v1 01/12] perf vendor events intel: Update alderlake events from 1.37 to 1.39 Ian Rogers
2026-05-29 4:51 ` [PATCH v1 02/12] perf vendor events intel: Update alderlaken " Ian Rogers
2026-05-29 4:51 ` [PATCH v1 03/12] perf vendor events intel: Update arrowlake events from 1.16 to 1.17 Ian Rogers
2026-05-29 4:51 ` [PATCH v1 04/12] perf vendor events intel: Update clearwaterforest events and metrics from 1.00 to 1.02 Ian Rogers
2026-05-29 4:51 ` [PATCH v1 05/12] perf vendor events intel: Update emeraldrapids events from 1.21 to 1.23 Ian Rogers
2026-05-29 4:51 ` Ian Rogers [this message]
2026-05-29 4:51 ` [PATCH v1 07/12] perf vendor events intel: Update graniterapids events from 1.17 to 1.18 Ian Rogers
2026-05-29 4:51 ` [PATCH v1 08/12] perf vendor events intel: Update lunarlake events from 1.21 to 1.22 Ian Rogers
2026-05-29 4:51 ` [PATCH v1 09/12] perf vendor events intel: Update meteorlake events from 1.20 to 1.21 Ian Rogers
2026-05-29 4:51 ` [PATCH v1 10/12] perf vendor events intel: Update pantherlake events from 1.04 to 1.05 Ian Rogers
2026-05-29 4:51 ` [PATCH v1 11/12] perf vendor events intel: Update sapphirerapids events from 1.36 to 1.39 Ian Rogers
2026-05-29 4:51 ` [PATCH v1 12/12] perf vendor events intel: Update sierraforest events from 1.15 to 1.17 Ian Rogers
2026-05-29 9:06 ` [PATCH v1 00/12] perf vendor events intel: update Mi, Dapeng
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260529045155.311805-7-irogers@google.com \
--to=irogers@google.com \
--cc=acme@kernel.org \
--cc=adrian.hunter@intel.com \
--cc=afaerber@suse.de \
--cc=alexander.shishkin@linux.intel.com \
--cc=dapeng1.mi@linux.intel.com \
--cc=james.clark@linaro.org \
--cc=jolsa@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-perf-users@vger.kernel.org \
--cc=mani@kernel.org \
--cc=mingo@redhat.com \
--cc=namhyung@kernel.org \
--cc=peterz@infradead.org \
--cc=thomas.falcon@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.