From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF361241C8C; Sat, 30 May 2026 18:39:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780166341; cv=none; b=t/p6tSAtv9UT3yHmjLqXNKJ16KYaljKmZH5w8rlRGxV5AE7LWAoMVsPtz/KVl5qiirPg2gav4RCBX5eqDhu0DBPulse3ZrpOB+0tcmJmcGGGo0A3SRgkU5nGfawoawB4z92GespuAuWUQ3KGHPMjAfCIkh2g63O+ff9w4FzE8V8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780166341; c=relaxed/simple; bh=G8Mbus5zWU4kr+nUKvZHcuUDxsEkuxZpi9NXdPOjwrI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WBlvCAIsAhQxUN6Kua/9WSr7rWK8o4sYgCewS0RE7LqwE9F7iSNrB6bytNBww1bTJKKwl4dG1SuPdPT7xJ9AxFJEtD5HiPXvIo0pnKl86BUxJxG2CXnPhaw0U1DV32JuvRn/Z1fLPGCAn5xrlt3MVrMj18N2T3/pXpLcVfmWUvI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=oFOMy9Wu; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="oFOMy9Wu" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1EBF71F00893; Sat, 30 May 2026 18:38:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1780166340; bh=KwqGu0gi852eQ5LrW+WGbBYnriIN0+ja0lqXhFJ7tf8=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=oFOMy9WuY/BtB3/5zLIuMC2tzWsywVHXVBsmnIHpi4CXLJIq89rv2acuYWzPmKRRj EgUejAiLdKXGxotpjbOHAL4huTYdtgiCJr31Jm41DBIUh5A085f4gl6XFWiRVVFBF/ /m0W+6rIysNu1Q794wIRo8yjECGXXIJT/W2Dllbs= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Connor Abbott , Rob Clark , Sasha Levin Subject: [PATCH 5.10 344/589] drm/msm/a6xx: Fix HLSQ register dumping Date: Sat, 30 May 2026 18:03:45 +0200 Message-ID: <20260530160233.926709791@linuxfoundation.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260530160224.570625122@linuxfoundation.org> References: <20260530160224.570625122@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 5.10-stable review patch. If anyone has any objections, please let me know. ------------------ From: Rob Clark [ Upstream commit c289a6db9ba6cb974f0317da142e4f665d589566 ] Fix the bitfield offset of HLSQ_READ_SEL state-type bitfield. Otherwise we are always reading TP state when we wanted SP or HLSQ state. Reported-by: Connor Abbott Suggested-by: Connor Abbott Fixes: 1707add81551 ("drm/msm/a6xx: Add a6xx gpu state") Signed-off-by: Rob Clark Patchwork: https://patchwork.freedesktop.org/patch/714236/ Message-ID: <20260325184043.1259312-1-robin.clark@oss.qualcomm.com> Signed-off-by: Sasha Levin --- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c index 0db27699025ab..6e9a3f843b3f5 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c @@ -642,7 +642,7 @@ static void a6xx_get_crashdumper_hlsq_registers(struct msm_gpu *gpu, u64 out = dumper->iova + A6XX_CD_DATA_OFFSET; int i, regcount = 0; - in += CRASHDUMP_WRITE(in, REG_A6XX_HLSQ_DBG_READ_SEL, regs->val1); + in += CRASHDUMP_WRITE(in, REG_A6XX_HLSQ_DBG_READ_SEL, (regs->val1 & 0xff) << 8); for (i = 0; i < regs->count; i += 2) { u32 count = RANGE(regs->registers, i); -- 2.53.0