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[23.244.200.70]) by smtp.gmail.com with ESMTPSA id af79cd13be357-9153244e114sm565606885a.5.2026.05.30.10.35.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 May 2026 10:35:33 -0700 (PDT) From: Joshua Milas To: tglx@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, pjw@kernel.org, samuel.holland@sifive.com, unicorn_wang@outlook.com, inochiama@gmail.com, daniel.lezcano@linaro.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, liujingqi@lanxincomputing.com, alexander.sverdlin@gmail.com, rabenda.cn@gmail.com, dlan@kernel.org, chao.wei@sophgo.com, anup@brainfault.org Cc: josh.milas@gmail.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, sophgo@lists.linux.dev, hanguidong02@gmail.com, michael.opdenacker@rootcommit.com Subject: [PATCH v5 RESEND 4/5] riscv64: dts: sophgo: add SG2000 dtsi Date: Sat, 30 May 2026 13:33:46 -0400 Message-ID: <20260530173347.33533-5-josh.milas@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260530173347.33533-1-josh.milas@gmail.com> References: <20260530173347.33533-1-josh.milas@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Adds sg2000.dtsi on the RISCV side. Signed-off-by: Joshua Milas --- arch/riscv/boot/dts/sophgo/sg2000.dtsi | 53 ++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/sg2000.dtsi diff --git a/arch/riscv/boot/dts/sophgo/sg2000.dtsi b/arch/riscv/boot/dts/sophgo/sg2000.dtsi new file mode 100644 index 0000000000000..412adacc00576 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/sg2000.dtsi @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16) + +#include +#include +#include "cv180x-cpus.dtsi" +#include "cv180x.dtsi" +#include "cv181x.dtsi" + +/ { + compatible = "sophgo,sg2000"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; + + soc { + interrupt-parent = <&plic>; + dma-noncoherent; + + pinctrl: pinctrl@3001000 { + compatible = "sophgo,sg2000-pinctrl"; + reg = <0x03001000 0x1000>, + <0x05027000 0x1000>; + reg-names = "sys", "rtc"; + }; + + clk: clock-controller@3002000 { + compatible = "sophgo,sg2000-clk"; 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[23.244.200.70]) by smtp.gmail.com with ESMTPSA id af79cd13be357-9153244e114sm565606885a.5.2026.05.30.10.35.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 May 2026 10:35:33 -0700 (PDT) From: Joshua Milas To: tglx@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, pjw@kernel.org, samuel.holland@sifive.com, unicorn_wang@outlook.com, inochiama@gmail.com, daniel.lezcano@linaro.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, liujingqi@lanxincomputing.com, alexander.sverdlin@gmail.com, rabenda.cn@gmail.com, dlan@kernel.org, chao.wei@sophgo.com, anup@brainfault.org Cc: josh.milas@gmail.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, sophgo@lists.linux.dev, hanguidong02@gmail.com, michael.opdenacker@rootcommit.com Subject: [PATCH v5 RESEND 4/5] riscv64: dts: sophgo: add SG2000 dtsi Date: Sat, 30 May 2026 13:33:46 -0400 Message-ID: <20260530173347.33533-5-josh.milas@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260530173347.33533-1-josh.milas@gmail.com> References: <20260530173347.33533-1-josh.milas@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260530_103534_988421_0E5855BB X-CRM114-Status: GOOD ( 10.18 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Adds sg2000.dtsi on the RISCV side. Signed-off-by: Joshua Milas --- arch/riscv/boot/dts/sophgo/sg2000.dtsi | 53 ++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/sg2000.dtsi diff --git a/arch/riscv/boot/dts/sophgo/sg2000.dtsi b/arch/riscv/boot/dts/sophgo/sg2000.dtsi new file mode 100644 index 0000000000000..412adacc00576 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/sg2000.dtsi @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16) + +#include +#include +#include "cv180x-cpus.dtsi" +#include "cv180x.dtsi" +#include "cv181x.dtsi" + +/ { + compatible = "sophgo,sg2000"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; + + soc { + interrupt-parent = <&plic>; + dma-noncoherent; + + pinctrl: pinctrl@3001000 { + compatible = "sophgo,sg2000-pinctrl"; + reg = <0x03001000 0x1000>, + <0x05027000 0x1000>; + reg-names = "sys", "rtc"; + }; + + clk: clock-controller@3002000 { + compatible = "sophgo,sg2000-clk"; + reg = <0x03002000 0x1000>; + clocks = <&osc>; + #clock-cells = <1>; + }; + + plic: interrupt-controller@70000000 { + compatible = "sophgo,sg2000-plic", "thead,c900-plic"; + reg = <0x70000000 0x4000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + riscv,ndev = <101>; + }; + + clint: timer@74000000 { + compatible = "sophgo,sg2000-clint", "thead,c900-clint"; + reg = <0x74000000 0x10000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; + }; + }; +}; -- 2.53.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv