From: Rosen Penev <rosenp@gmail.com>
To: linux-input@vger.kernel.org
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>,
chleroy@kernel.org, Michal Simek <michal.simek@amd.com>,
linux-kernel@vger.kernel.org (open list),
linux-arm-kernel@lists.infradead.org (moderated list:ARM/ZYNQ
ARCHITECTURE)
Subject: [PATCH] Input: xilinx_ps2 - replace in_be32/out_be32 with ioread32be/iowrite32be
Date: Mon, 1 Jun 2026 20:59:07 -0700 [thread overview]
Message-ID: <20260602035907.623599-1-rosenp@gmail.com> (raw)
Mechanical conversion of the ppc4xx-specific accessors to the generic
portable helpers.
Allows enabling COMPILE_TEST for extra compile coverage.
Assisted-by: opencode:big-pickle
Signed-off-by: Rosen Penev <rosenp@gmail.com>
---
drivers/input/serio/Kconfig | 2 +-
drivers/input/serio/xilinx_ps2.c | 24 ++++++++++++------------
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/input/serio/Kconfig b/drivers/input/serio/Kconfig
index 5f15a6462056..60d886631c42 100644
--- a/drivers/input/serio/Kconfig
+++ b/drivers/input/serio/Kconfig
@@ -190,7 +190,7 @@ config SERIO_RAW
config SERIO_XILINX_XPS_PS2
tristate "Xilinx XPS PS/2 Controller Support"
- depends on PPC || MICROBLAZE
+ depends on PPC || MICROBLAZE || COMPILE_TEST
help
This driver supports XPS PS/2 IP from the Xilinx EDK on
PowerPC platform.
diff --git a/drivers/input/serio/xilinx_ps2.c b/drivers/input/serio/xilinx_ps2.c
index 411d55ca1a66..7eb96375b515 100644
--- a/drivers/input/serio/xilinx_ps2.c
+++ b/drivers/input/serio/xilinx_ps2.c
@@ -89,9 +89,9 @@ static int xps2_recv(struct xps2data *drvdata, u8 *byte)
int status = -1;
/* If there is data available in the PS/2 receiver, read it */
- sr = in_be32(drvdata->base_address + XPS2_STATUS_OFFSET);
+ sr = ioread32be(drvdata->base_address + XPS2_STATUS_OFFSET);
if (sr & XPS2_STATUS_RX_FULL) {
- *byte = in_be32(drvdata->base_address + XPS2_RX_DATA_OFFSET);
+ *byte = ioread32be(drvdata->base_address + XPS2_RX_DATA_OFFSET);
status = 0;
}
@@ -109,8 +109,8 @@ static irqreturn_t xps2_interrupt(int irq, void *dev_id)
int status;
/* Get the PS/2 interrupts and clear them */
- intr_sr = in_be32(drvdata->base_address + XPS2_IPISR_OFFSET);
- out_be32(drvdata->base_address + XPS2_IPISR_OFFSET, intr_sr);
+ intr_sr = ioread32be(drvdata->base_address + XPS2_IPISR_OFFSET);
+ iowrite32be(intr_sr, drvdata->base_address + XPS2_IPISR_OFFSET);
/* Check which interrupt is active */
if (intr_sr & XPS2_IPIXR_RX_OVF)
@@ -160,11 +160,11 @@ static int sxps2_write(struct serio *pserio, unsigned char c)
guard(spinlock_irqsave)(&drvdata->lock);
/* If the PS/2 transmitter is empty send a byte of data */
- sr = in_be32(drvdata->base_address + XPS2_STATUS_OFFSET);
+ sr = ioread32be(drvdata->base_address + XPS2_STATUS_OFFSET);
if (sr & XPS2_STATUS_TX_FULL)
return -EAGAIN;
- out_be32(drvdata->base_address + XPS2_TX_DATA_OFFSET, c);
+ iowrite32be(c, drvdata->base_address + XPS2_TX_DATA_OFFSET);
return 0;
}
@@ -189,8 +189,8 @@ static int sxps2_open(struct serio *pserio)
}
/* start reception by enabling the interrupts */
- out_be32(drvdata->base_address + XPS2_GIER_OFFSET, XPS2_GIER_GIE_MASK);
- out_be32(drvdata->base_address + XPS2_IPIER_OFFSET, XPS2_IPIXR_RX_ALL);
+ iowrite32be(XPS2_GIER_GIE_MASK, drvdata->base_address + XPS2_GIER_OFFSET);
+ iowrite32be(XPS2_IPIXR_RX_ALL, drvdata->base_address + XPS2_IPIER_OFFSET);
(void)xps2_recv(drvdata, &c);
return 0; /* success */
@@ -207,8 +207,8 @@ static void sxps2_close(struct serio *pserio)
struct xps2data *drvdata = pserio->port_data;
/* Disable the PS2 interrupts */
- out_be32(drvdata->base_address + XPS2_GIER_OFFSET, 0x00);
- out_be32(drvdata->base_address + XPS2_IPIER_OFFSET, 0x00);
+ iowrite32be(0x00, drvdata->base_address + XPS2_GIER_OFFSET);
+ iowrite32be(0x00, drvdata->base_address + XPS2_IPIER_OFFSET);
free_irq(drvdata->irq, drvdata);
}
@@ -278,13 +278,13 @@ static int xps2_of_probe(struct platform_device *ofdev)
}
/* Disable all the interrupts, just in case */
- out_be32(drvdata->base_address + XPS2_IPIER_OFFSET, 0);
+ iowrite32be(0, drvdata->base_address + XPS2_IPIER_OFFSET);
/*
* Reset the PS2 device and abort any current transaction,
* to make sure we have the PS2 in a good state.
*/
- out_be32(drvdata->base_address + XPS2_SRST_OFFSET, XPS2_SRST_RESET);
+ iowrite32be(XPS2_SRST_RESET, drvdata->base_address + XPS2_SRST_OFFSET);
dev_info(dev, "Xilinx PS2 at 0x%08llX mapped to 0x%p, irq=%d\n",
(unsigned long long)phys_addr, drvdata->base_address,
--
2.54.0
next reply other threads:[~2026-06-02 3:59 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-02 3:59 Rosen Penev [this message]
2026-06-02 4:10 ` [PATCH] Input: xilinx_ps2 - replace in_be32/out_be32 with ioread32be/iowrite32be sashiko-bot
2026-06-02 6:23 ` Michal Simek
2026-06-02 8:27 ` Rosen Penev
2026-06-02 8:34 ` Michal Simek
2026-06-02 8:51 ` Rosen Penev
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260602035907.623599-1-rosenp@gmail.com \
--to=rosenp@gmail.com \
--cc=chleroy@kernel.org \
--cc=dmitry.torokhov@gmail.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-input@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=michal.simek@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.