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envelope-from=cp0613@linux.alibaba.com; helo=out30-133.freemail.mail.aliyun.com X-Spam_score_int: -166 X-Spam_score: -16.7 X-Spam_bar: ---------------- X-Spam_report: (-16.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Enable CXL support on the RISC-V virt machine following the same approach used by the ARM virt machine: - Add PXB and ACPI_CXL Kconfig selections - Add CXLState and PCIBus pointer to RISCVVirtState - Register CXL machine properties via cxl_machine_init() - Create CXL host register region above the PCIe high MMIO region - Call cxl_hook_up_pxb_registers() and cxl_fmws_link_targets() at machine_done time - Map Fixed Memory Windows above the CXL host register region - Add ACPI0017 device in DSDT and build CEDT table in virt-acpi-build.c Signed-off-by: Chen Pei --- hw/riscv/Kconfig | 2 ++ hw/riscv/virt-acpi-build.c | 20 ++++++++++++++++++ hw/riscv/virt.c | 42 ++++++++++++++++++++++++++++++++++++++ include/hw/riscv/virt.h | 3 +++ 4 files changed, 67 insertions(+) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 2518b04175..ebd0355f09 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -66,8 +66,10 @@ config RISCV_VIRT select VIRTIO_MMIO select FW_CFG_DMA select PLATFORM_BUS + select PXB select ACPI select ACPI_PCI + select ACPI_CXL config SHAKTI_C bool diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index 413d47d70e..309d64b322 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -29,12 +29,16 @@ #include "hw/acpi/aml-build.h" #include "hw/acpi/pci.h" #include "hw/acpi/utils.h" +#include "hw/acpi/cxl.h" #include "hw/intc/riscv_aclint.h" #include "hw/nvram/fw_cfg_acpi.h" #include "hw/pci-host/gpex.h" +#include "hw/pci/pci_bus.h" #include "hw/riscv/virt.h" #include "hw/riscv/numa.h" #include "hw/virtio/virtio-acpi.h" +#include "hw/cxl/cxl.h" +#include "hw/cxl/cxl_host.h" #include "kvm/kvm_riscv.h" #include "migration/vmstate.h" #include "qapi/error.h" @@ -503,6 +507,17 @@ static void build_dsdt(GArray *table_data, acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES * 2); } + if (s->cxl_devices_state.is_enabled) { + Aml *cxl_dev = aml_device("CXLM"); + aml_append(cxl_dev, aml_name_decl("_HID", aml_string("ACPI0017"))); + Aml *method = aml_method("_STA", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_int(0x0B))); + aml_append(cxl_dev, method); + build_cxl_dsm_method(cxl_dev); + + aml_append(scope, cxl_dev); + } + aml_append(dsdt, scope); /* copy AML table into ACPI tables blob and patch header there */ @@ -910,6 +925,11 @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables) s->oem_table_id); } + if (s->cxl_devices_state.is_enabled) { + cxl_build_cedt(table_offsets, tables_blob, tables->linker, + s->oem_id, s->oem_table_id, &s->cxl_devices_state); + } + if (ms->numa_state->num_nodes > 0) { acpi_add_table(table_offsets, tables_blob); build_srat(tables_blob, tables->linker, s); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index ce64eaaef7..899f632de7 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -55,6 +55,8 @@ #include "hw/pci/pci.h" #include "hw/pci-host/gpex.h" #include "hw/display/ramfb.h" +#include "hw/cxl/cxl.h" +#include "hw/cxl/cxl_host.h" #include "hw/acpi/aml-build.h" #include "qapi/qapi-visit-common.h" #include "hw/virtio/virtio-iommu.h" @@ -1259,9 +1261,27 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, } GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(dev)->bus; + s->bus = PCI_HOST_BRIDGE(dev)->bus; return dev; } +static void create_cxl_host_reg_region(RISCVVirtState *s) +{ + MemoryRegion *sysmem = get_system_memory(); + MemoryRegion *mr = &s->cxl_devices_state.host_mr; + hwaddr base; + + if (!s->cxl_devices_state.is_enabled) { + return; + } + + base = virt_high_pcie_memmap.base + virt_high_pcie_memmap.size; + base = ROUND_UP(base, 64 * KiB); + + memory_region_init(mr, OBJECT(s), "cxl_host_reg", 64 * KiB * 16); + memory_region_add_subregion(sysmem, base, mr); +} + static FWCfgState *create_fw_cfg(const MachineState *ms, hwaddr base) { FWCfgState *fw_cfg; @@ -1426,6 +1446,15 @@ static void virt_machine_done(Notifier *notifier, void *data) machine_done); MachineState *machine = MACHINE(s); hwaddr start_addr = s->memmap[VIRT_DRAM].base; + + if (s->bus) { + cxl_hook_up_pxb_registers(s->bus, &s->cxl_devices_state, + &error_fatal); + } + + if (s->cxl_devices_state.is_enabled) { + cxl_fmws_link_targets(&error_fatal); + } hwaddr firmware_end_addr; vaddr kernel_start_addr; const char *firmware_name = riscv_default_firmware_name(&s->soc[0]); @@ -1663,6 +1692,17 @@ static void virt_machine_init(MachineState *machine) ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); } + create_cxl_host_reg_region(s); + + if (s->cxl_devices_state.is_enabled) { + hwaddr cxl_base = virt_high_pcie_memmap.base + + virt_high_pcie_memmap.size; + cxl_base += memory_region_size(&s->cxl_devices_state.host_mr); + cxl_base = ROUND_UP(cxl_base, 256 * MiB); + cxl_fmws_set_memmap(cxl_base, UINT64_MAX); + cxl_fmws_update_mmio(); + } + /* register system main memory (actual RAM) */ memory_region_add_subregion(system_memory, s->memmap[VIRT_DRAM].base, machine->ram); @@ -1769,6 +1809,8 @@ static void virt_machine_instance_init(Object *obj) s->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); s->acpi = ON_OFF_AUTO_AUTO; s->iommu_sys = ON_OFF_AUTO_AUTO; + + cxl_machine_init(obj, &s->cxl_devices_state); } static char *virt_get_aia_guests(Object *obj, Error **errp) diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 18a2a323a3..c3201588bb 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -24,6 +24,7 @@ #include "hw/core/sysbus.h" #include "hw/block/flash.h" #include "hw/intc/riscv_imsic.h" +#include "hw/cxl/cxl.h" #define VIRT_CPUS_MAX_BITS 9 #define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS) @@ -64,6 +65,8 @@ struct RISCVVirtState { struct GPEXHost *gpex_host; OnOffAuto iommu_sys; uint16_t pci_iommu_bdf; + CXLState cxl_devices_state; + PCIBus *bus; }; enum { -- 2.50.1