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list:ASPEED BMCs" , "open list:All patches CC here" CC: Jamin Lin , Troy Lee Subject: [PATCH v3 01/10] hw/i2c/aspeed_i2c: Introduce dma_addr_lo_mask to unify DMA address handling Thread-Topic: [PATCH v3 01/10] hw/i2c/aspeed_i2c: Introduce dma_addr_lo_mask to unify DMA address handling Thread-Index: AQHc8w2E8LG9mTwF50q43NKlevPhtg== Date: Wed, 3 Jun 2026 04:00:29 +0000 Message-ID: <20260603040027.938816-2-jamin_lin@aspeedtech.com> References: <20260603040027.938816-1-jamin_lin@aspeedtech.com> In-Reply-To: <20260603040027.938816-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: TYZPR06MB4980:EE_|TYSPR06MB6921:EE_ x-ms-office365-filtering-correlation-id: 84178ad2-4847-490f-58f9-08dec124a706 x-ms-exchange-senderadcheck: 1 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X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYSPR06MB6921 Received-SPF: pass client-ip=2a01:111:f403:c405::5; envelope-from=jamin_lin@aspeedtech.com; helo=TYPPR03CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org The Aspeed I2C controller has two register layouts.=0A= =0A= The AST2500 uses the old mode with a single DMA address register (I2CD_DMA_= ADDR)=0A= where the address is 4-byte aligned and masked to 0x3ffffffc.=0A= =0A= >From AST2600 onwards, the new mode provides separate master TX/RX and slave= RX DMA=0A= address registers (I2CM_DMA_TX_ADDR, I2CM_DMA_RX_ADDR, I2CS_DMA_RX_ADDR)=0A= with different address widths per SoC:=0A= AST2600 (new mode): 0x7fffffff - bits[30:0]=0A= AST1030 (new mode): 0x7fffffff - bits[30:0]=0A= AST1060 (new mode): 0x7fffffff - bits[30:0]=0A= AST2700 (new mode): 0xffffffff - bits[31:0]=0A= =0A= Introduce dma_addr_lo_mask as a per-class attribute and apply it=0A= uniformly when storing DMA address register writes and when loading=0A= the address into dma_dram_offset for both master and slave paths.=0A= This replaces the previous FIELD_EX32 extractions (which incorrectly=0A= stripped bit 31 on AST2700) and the hardcoded 0x3ffffffc literal in=0A= the old-mode path.=0A= =0A= Fixes: 1809ab6a67359e0876981cd05d2a50b2843eabad ("hw/i2c/aspeed: Add AST270= 0 support")=0A= Signed-off-by: Jamin Lin =0A= ---=0A= include/hw/i2c/aspeed_i2c.h | 5 +----=0A= hw/i2c/aspeed_i2c.c | 24 ++++++++++++++----------=0A= 2 files changed, 15 insertions(+), 14 deletions(-)=0A= =0A= diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h=0A= index d42cb4865a..1fc229f699 100644=0A= --- a/include/hw/i2c/aspeed_i2c.h=0A= +++ b/include/hw/i2c/aspeed_i2c.h=0A= @@ -209,13 +209,9 @@ REG32(I2CS_DMA_LEN, 0x2c)=0A= FIELD(I2CS_DMA_LEN, TX_BUF_LEN_W1T, 15, 1)=0A= FIELD(I2CS_DMA_LEN, TX_BUF_LEN, 0, 11)=0A= REG32(I2CM_DMA_TX_ADDR, 0x30)=0A= - FIELD(I2CM_DMA_TX_ADDR, ADDR, 0, 31)=0A= REG32(I2CM_DMA_RX_ADDR, 0x34)=0A= - FIELD(I2CM_DMA_RX_ADDR, ADDR, 0, 31)=0A= REG32(I2CS_DMA_TX_ADDR, 0x38)=0A= - FIELD(I2CS_DMA_TX_ADDR, ADDR, 0, 31)=0A= REG32(I2CS_DMA_RX_ADDR, 0x3c)=0A= - FIELD(I2CS_DMA_RX_ADDR, ADDR, 0, 31)=0A= REG32(I2CS_DEV_ADDR, 0x40)=0A= REG32(I2CM_DMA_LEN_STS, 0x48)=0A= FIELD(I2CM_DMA_LEN_STS, RX_LEN, 16, 13)=0A= @@ -303,6 +299,7 @@ struct AspeedI2CClass {=0A= bool has_share_pool;=0A= uint64_t mem_size;=0A= bool has_dma64;=0A= + uint32_t dma_addr_lo_mask;=0A= };=0A= =0A= static inline bool aspeed_i2c_is_new_mode(AspeedI2CState *s)=0A= diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c=0A= index 4a6732a185..9d4e72c858 100644=0A= --- a/hw/i2c/aspeed_i2c.c=0A= +++ b/hw/i2c/aspeed_i2c.c=0A= @@ -236,7 +236,7 @@ static void aspeed_i2c_set_tx_dma_dram_offset(AspeedI2C= Bus *bus)=0A= value =3D bus->regs[R_I2CM_DMA_TX_ADDR];=0A= bus->dma_dram_offset =3D=0A= deposit64(bus->dma_dram_offset, 0, 32,=0A= - FIELD_EX32(value, I2CM_DMA_TX_ADDR, ADDR));=0A= + value & aic->dma_addr_lo_mask);=0A= if (aic->has_dma64) {=0A= value =3D bus->regs[R_I2CM_DMA_TX_ADDR_HI];=0A= bus->dma_dram_offset =3D=0A= @@ -246,7 +246,7 @@ static void aspeed_i2c_set_tx_dma_dram_offset(AspeedI2C= Bus *bus)=0A= } else {=0A= value =3D bus->regs[R_I2CD_DMA_ADDR];=0A= bus->dma_dram_offset =3D deposit64(bus->dma_dram_offset, 0, 32,=0A= - value & 0x3ffffffc);=0A= + value & aic->dma_addr_lo_mask);= =0A= }=0A= }=0A= =0A= @@ -261,7 +261,7 @@ static void aspeed_i2c_set_rx_dma_dram_offset(AspeedI2C= Bus *bus)=0A= value =3D bus->regs[R_I2CM_DMA_RX_ADDR];=0A= bus->dma_dram_offset =3D=0A= deposit64(bus->dma_dram_offset, 0, 32,=0A= - FIELD_EX32(value, I2CM_DMA_RX_ADDR, ADDR));=0A= + value & aic->dma_addr_lo_mask);=0A= if (aic->has_dma64) {=0A= value =3D bus->regs[R_I2CM_DMA_RX_ADDR_HI];=0A= bus->dma_dram_offset =3D=0A= @@ -271,7 +271,7 @@ static void aspeed_i2c_set_rx_dma_dram_offset(AspeedI2C= Bus *bus)=0A= } else {=0A= value =3D bus->regs[R_I2CD_DMA_ADDR];=0A= bus->dma_dram_offset =3D deposit64(bus->dma_dram_offset, 0, 32,=0A= - value & 0x3ffffffc);=0A= + value & aic->dma_addr_lo_mask);= =0A= }=0A= }=0A= =0A= @@ -735,12 +735,10 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bu= s, hwaddr offset,=0A= aspeed_i2c_bus_raise_interrupt(bus);=0A= break;=0A= case A_I2CM_DMA_TX_ADDR:=0A= - bus->regs[R_I2CM_DMA_TX_ADDR] =3D FIELD_EX32(value, I2CM_DMA_TX_AD= DR,=0A= - ADDR);=0A= + bus->regs[R_I2CM_DMA_TX_ADDR] =3D value & aic->dma_addr_lo_mask;= =0A= break;=0A= case A_I2CM_DMA_RX_ADDR:=0A= - bus->regs[R_I2CM_DMA_RX_ADDR] =3D FIELD_EX32(value, I2CM_DMA_RX_AD= DR,=0A= - ADDR);=0A= + bus->regs[R_I2CM_DMA_RX_ADDR] =3D value & aic->dma_addr_lo_mask;= =0A= break;=0A= case A_I2CM_DMA_LEN:=0A= w1t =3D FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN_W1T) ||=0A= @@ -777,7 +775,7 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus,= hwaddr offset,=0A= bus->regs[R_I2CS_DEV_ADDR] =3D value;=0A= break;=0A= case A_I2CS_DMA_RX_ADDR:=0A= - bus->regs[R_I2CS_DMA_RX_ADDR] =3D value;=0A= + bus->regs[R_I2CS_DMA_RX_ADDR] =3D value & aic->dma_addr_lo_mask;= =0A= break;=0A= case A_I2CS_DMA_LEN:=0A= if (FIELD_EX32(value, I2CS_DMA_LEN, RX_BUF_LEN_W1T)) {=0A= @@ -1375,6 +1373,8 @@ static void aspeed_i2c_class_init(ObjectClass *klass,= const void *data)=0A= static int aspeed_i2c_bus_new_slave_event(AspeedI2CBus *bus,=0A= enum i2c_event event)=0A= {=0A= + AspeedI2CClass *aic =3D ASPEED_I2C_GET_CLASS(bus->controller);=0A= +=0A= switch (event) {=0A= case I2C_START_SEND_ASYNC:=0A= if (!SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CS_CMD, RX_DMA_EN)) {= =0A= @@ -1385,7 +1385,7 @@ static int aspeed_i2c_bus_new_slave_event(AspeedI2CBu= s *bus,=0A= ARRAY_FIELD_DP32(bus->regs, I2CS_DMA_LEN_STS, RX_LEN, 0);=0A= bus->dma_dram_offset =3D=0A= deposit64(bus->dma_dram_offset, 0, 32,=0A= - ARRAY_FIELD_EX32(bus->regs, I2CS_DMA_RX_ADDR, ADDR))= ;=0A= + bus->regs[R_I2CS_DMA_RX_ADDR] & aic->dma_addr_lo_mas= k);=0A= bus->regs[R_I2CC_DMA_LEN] =3D=0A= ARRAY_FIELD_EX32(bus->regs, I2CS_DMA_LEN, RX_BUF_LEN) + 1;=0A= i2c_ack(bus->bus);=0A= @@ -1608,6 +1608,7 @@ static void aspeed_2500_i2c_class_init(ObjectClass *k= lass, const void *data)=0A= aic->check_sram =3D true;=0A= aic->has_dma =3D true;=0A= aic->mem_size =3D 0x1000;=0A= + aic->dma_addr_lo_mask =3D 0x3ffffffc;=0A= }=0A= =0A= static qemu_irq aspeed_2600_i2c_bus_get_irq(AspeedI2CBus *bus)=0A= @@ -1631,6 +1632,7 @@ static void aspeed_2600_i2c_class_init(ObjectClass *k= lass, const void *data)=0A= aic->bus_pool_base =3D aspeed_2500_i2c_bus_pool_base;=0A= aic->has_dma =3D true;=0A= aic->mem_size =3D 0x1000;=0A= + aic->dma_addr_lo_mask =3D 0x7fffffff;=0A= }=0A= =0A= static void aspeed_1030_i2c_class_init(ObjectClass *klass, const void *dat= a)=0A= @@ -1649,6 +1651,7 @@ static void aspeed_1030_i2c_class_init(ObjectClass *k= lass, const void *data)=0A= aic->bus_pool_base =3D aspeed_2500_i2c_bus_pool_base;=0A= aic->has_dma =3D true;=0A= aic->mem_size =3D 0x10000;=0A= + aic->dma_addr_lo_mask =3D 0x7fffffff;=0A= }=0A= =0A= static void aspeed_2700_i2c_class_init(ObjectClass *klass, const void *dat= a)=0A= @@ -1670,6 +1673,7 @@ static void aspeed_2700_i2c_class_init(ObjectClass *k= lass, const void *data)=0A= aic->has_dma =3D true;=0A= aic->mem_size =3D 0x2000;=0A= aic->has_dma64 =3D true;=0A= + aic->dma_addr_lo_mask =3D 0xffffffff;=0A= }=0A= =0A= static const TypeInfo aspeed_i2c_types[] =3D {=0A= -- =0A= 2.43.0=0A=