[PATCH v3 07/10] hw/i2c/aspeed_i2c: Introduce AST1040 I2C model

[Jamin Lin <jamin_lin@aspeedtech.com>]

Introduce the AST1040 I2C controller model.

The AST1040 I2C controller is compatible with the AST2700 I2C controller,
including DMA support and the 64-bit DMA address registers. Set has_dma64 so
firmware can access the high address register and program it to zero, as the
CM4 CPU only supports 32-bit addressing.

AST1040 has 14 I2C buses and its HyperRAM is limited to 16 MiB,
so restrict the DMA low address mask to 0x00ffffff.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---
 include/hw/i2c/aspeed_i2c.h |  1 +
 hw/i2c/aspeed_i2c.c         | 33 +++++++++++++++++++++++++++++++++
 2 files changed, 34 insertions(+)

diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h
index b2e4d2fb9d..156998e7c1 100644
--- a/include/hw/i2c/aspeed_i2c.h
+++ b/include/hw/i2c/aspeed_i2c.h
@@ -30,6 +30,7 @@
 #define TYPE_ASPEED_2500_I2C TYPE_ASPEED_I2C "-ast2500"
 #define TYPE_ASPEED_2600_I2C TYPE_ASPEED_I2C "-ast2600"
 #define TYPE_ASPEED_1030_I2C TYPE_ASPEED_I2C "-ast1030"
+#define TYPE_ASPEED_1040_I2C TYPE_ASPEED_I2C "-ast1040"
 #define TYPE_ASPEED_2700_I2C TYPE_ASPEED_I2C "-ast2700"
 OBJECT_DECLARE_TYPE(AspeedI2CState, AspeedI2CClass, ASPEED_I2C)
 
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index 856d5dc1db..27afcaecee 100644
--- a/hw/i2c/aspeed_i2c.c
+++ b/hw/i2c/aspeed_i2c.c
@@ -1654,6 +1654,34 @@ static void aspeed_1030_i2c_class_init(ObjectClass *klass, const void *data)
     aic->dma_addr_lo_mask = 0x7fffffff;
 }
 
+static void aspeed_1040_i2c_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass);
+
+    dc->desc = "ASPEED 1040 I2C Controller";
+
+    /*
+     * AST1040 reuses the AST2700 I2C controller implementation since
+     * the AST1040 is compatible with AST2700. AST1040 has 14 I2C buses,
+     * and its HyperRAM is limited to 16 MiB, so the DMA low address
+     * mask is restricted accordingly.
+     */
+    aic->num_busses = 14;
+    aic->reg_size = 0xa0;
+    aic->reg_gap_size = 0x60;
+    aic->gap = -1; /* no gap */
+    aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq;
+    aic->pool_size = 0x40;
+    aic->pool_gap_size = 0xc0;
+    aic->pool_base = 0x1c0;
+    aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base;
+    aic->has_dma = true;
+    aic->mem_size = 0x2000;
+    aic->has_dma64 = true;
+    aic->dma_addr_lo_mask = 0x00ffffff;
+}
+
 static void aspeed_2700_i2c_class_init(ObjectClass *klass, const void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
@@ -1703,6 +1731,11 @@ static const TypeInfo aspeed_i2c_types[] = {
         .parent = TYPE_ASPEED_I2C,
         .class_init = aspeed_1030_i2c_class_init,
     },
+    {
+        .name = TYPE_ASPEED_1040_I2C,
+        .parent = TYPE_ASPEED_I2C,
+        .class_init = aspeed_1040_i2c_class_init,
+    },
     {
         .name = TYPE_ASPEED_2400_I2C,
         .parent = TYPE_ASPEED_I2C,
-- 
2.43.0