[PATCH 2/4] imx9: scmi: Print CPU part number name

[Ye Li <ye.li@nxp.com>]

Decode the CPU part number from PART_NUM fuse and print it in CPU name.

For iMX95 and iMX952 Part number fuse is defined as:
[7:6] : Package description
[5:2] : Segment
[1:0] : Number of A55 cores

For iMX94, the PART_NUM[7:0] fuse directly reflects the
part number value.

Signed-off-by: Ye Li <ye.li@nxp.com>
---
 arch/arm/mach-imx/imx9/scmi/soc.c | 88 ++++++++++++++++++++++++++++---
 drivers/cpu/imx8_cpu.c            | 12 ++++-
 2 files changed, 92 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c
index 76b6870620b..aedaa0d4bca 100644
--- a/arch/arm/mach-imx/imx9/scmi/soc.c
+++ b/arch/arm/mach-imx/imx9/scmi/soc.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2025 NXP
+ * Copyright 2025-2026 NXP
  *
  * Peng Fan <peng.fan@nxp.com>
  */
@@ -709,14 +709,88 @@ int get_reset_reason(bool sys, bool lm)
 	return 0;
 }
 
-const char *get_imx_type(u32 imxtype)
+const char *get_cpu_variant_type_name(u32 type)
 {
-	switch (imxtype) {
-	case SCMI_CPU:
-		return IMX_PLAT_STR;
-	default:
-		return "??";
+	u32 val, core_num, part_num;
+	int ret;
+
+	ret = fuse_read(2, 1, &val);
+	if (ret)
+		return NULL;
+
+	/* Get part num */
+	part_num = (val >> 4) & 0xff;
+	if (!part_num)
+		return NULL;
+
+	if (type == MXC_CPU_IMX95 || type == MXC_CPU_IMX952) {
+		u32 segment;
+		static char name[8] = "95294";
+		char pn[2];
+
+		core_num = part_num & 0x3;
+		segment = (part_num >> 2) & 0xf;
+
+		switch (segment) {
+		case 0xa:
+			pn[0] = 'T';
+			break;
+		case 0xb:
+			pn[0] = 'V';
+			break;
+		case 0xc:
+			pn[0] = 'C';
+			break;
+		case 0xd:
+			pn[0] = 'G';
+			break;
+		case 0xe:
+			pn[0] = 'I';
+			break;
+		case 0xf:
+			pn[0] = 'N';
+			break;
+		default:
+			pn[0] = segment + '0';
+			break;
+		}
+
+		pn[1] = core_num * 2 + '0';
+
+		if (type == MXC_CPU_IMX95)
+			sprintf(name, "95%c%c", pn[0], pn[1]);
+		else
+			sprintf(name, "952%c%c", pn[0], pn[1]);
+
+		return name;
+	} else if (type == MXC_CPU_IMX94) {
+		static char *name = "94398";
+
+		core_num = 8;
+
+		ret = fuse_read(2, 2, &val);
+		if (ret)
+			return NULL;
+
+		if (part_num > 30) { /* 943 */
+			/* A55 2 & 3 disabled */
+			if ((val & 0x18) == 0x18)
+				core_num = 6;
+		} else if (part_num > 20) { /* 942 */
+			core_num = 5;
+
+			/* m7_0 disabled */
+			if ((val & 0x200) == 0x200)
+				core_num = 4;
+		} else if (part_num > 10) { /* 941 */
+			core_num = 5;
+		}
+		sprintf(name, "94%u%u", part_num, core_num);
+
+		return name;
 	}
+
+	return NULL;
 }
 
 void build_info(void)
diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c
index 2bd76ffa739..7bb7b420176 100644
--- a/drivers/cpu/imx8_cpu.c
+++ b/drivers/cpu/imx8_cpu.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2019, 2024 NXP
+ * Copyright 2019, 2024-2026 NXP
  */
 
 #include <cpu.h>
@@ -28,8 +28,18 @@ struct cpu_imx_plat {
 	u32 mpidr;
 };
 
+__weak const char *get_cpu_variant_type_name(u32 type)
+{
+	return NULL;
+}
+
 static const char *get_imx_type_str(u32 imxtype)
 {
+	const char *name = get_cpu_variant_type_name(imxtype);
+
+	if (name)
+		return name;
+
 	switch (imxtype) {
 	case MXC_CPU_IMX8MM:
 		return "8MMQ";	/* Quad-core version of the imx8mm */
-- 
2.50.1