Re: [PATCH v2 06/12] arm64: dts: imx8mp-var-som-symphony: enable PCIe

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Missing PERST# reset signal configuration for the PCIe slot.
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commit 2705091bb2c968ad6e44f8cd4b794c2f5e63b41c
Author: Stefano Radaelli <stefano.r@variscite.com>

arm64: dts: imx8mp-var-som-symphony: enable PCIe
    
This commit adds the PCIe reference clock and enables the PCIe controller
and PHY nodes on the i.MX8MP Symphony carrier board.

> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts
> index 9500c9bf0f421..a928dc2d9adce 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts

[ ... ]

> @@ -146,6 +152,17 @@ rtc@68 {
>  	};
>  };
>  
> +&pcie {
> +	status = "okay";
> +};

[Severity: High]
Will this configuration successfully enumerate PCIe endpoints on the Symphony
carrier board without the reset-gpios property?

The Symphony baseboard typically routes the PCIe slot's PERST# signal to pin
1 of the pcal6408 I2C GPIO expander (as seen on the shared imx8mm symphony
board layout). Without configuring reset-gpios = <&pcal6408 1 GPIO_ACTIVE_LOW>;
here, the host driver in drivers/pci/controller/dwc/pci-imx6.c might not be
able to fetch and de-assert the reset signal.

Could this leave connected PCIe endpoint devices held in hardware reset?

> +
> +&pcie_phy {
> +	clocks = <&pcie0_refclk>;
> +	clock-names = "ref";
> +	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
> +	status = "okay";
> +};

[ ... ]

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Sashiko AI review · https://sashiko.dev/#/patchset/cover.1780492180.git.stefano.r@variscite.com?part=6