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[211.75.127.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c164fa0236sm86673185ad.33.2026.06.05.01.50.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Jun 2026 01:50:51 -0700 (PDT) Received: from hqs-appsw-a2o.mp600.macronix.com (unknown [172.17.236.67]) by twhmp6px (Postfix) with ESMTPS id AD5854163B72; Fri, 5 Jun 2026 16:50:49 +0800 (CST) From: Cheng Ming Lin To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, alvinzhou@mxic.com.tw, Cheng Ming Lin Subject: [PATCH v3 1/2] mtd: spi-nor: Add support for MX25L12833F and MX25L12845G Date: Fri, 5 Jun 2026 16:48:36 +0800 Message-Id: <20260605084837.1875896-2-linchengming884@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260605084837.1875896-1-linchengming884@gmail.com> References: <20260605084837.1875896-1-linchengming884@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260605_015053_140788_17C3B272 X-CRM114-Status: GOOD ( 14.13 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org From: Cheng Ming Lin Add support for Macronix MX25L12833F and MX25L12845G SPI NOR flashes. These parts share the same JEDEC ID (0xc2, 0x20, 0x18) as the legacy MX25L12805D. The newer flashes support SFDP and 1-4-4 Page Program in 3-byte address mode, but this 4PP capability is not defined in their SFDP tables. Conversely, the legacy MX25L12805D lacks SFDP support entirely and does not support 4PP. To safely enable 4PP for the newer flashes without breaking the legacy part, introduce a post_sfdp fixup. Since the legacy MX25L12805D does not support SFDP, it falls back to static parameters and will never execute the post_sfdp hook. The newer flashes will successfully parse the SFDP, trigger the hook, and safely append the SNOR_HWCAPS_PP_1_4_4 capability. Signed-off-by: Cheng Ming Lin --- drivers/mtd/spi-nor/macronix.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c index e97f5cbd9..1adb79832 100644 --- a/drivers/mtd/spi-nor/macronix.c +++ b/drivers/mtd/spi-nor/macronix.c @@ -83,6 +83,25 @@ mx25l3255e_late_init_fixups(struct spi_nor *nor) return 0; } +static int +mx25l12805d_4pp3b_post_sfdp_fixups(struct spi_nor *nor) +{ + struct spi_nor_flash_parameter *params = nor->params; + + /* + * JEDEC ID 0xc22018 is shared by MX25L12805D (no SFDP, no 4PP) and + * MX25L12833F/MX25L12845G (support SFDP and 4PP in 3-byte mode). + * The legacy 05D lacks SFDP and will not execute this hook. For + * the newer flashes, 3-byte 1-4-4 PP is not defined in SFDP, so + * we safely enable it here. + */ + params->hwcaps.mask |= SNOR_HWCAPS_PP_1_4_4; + spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_4_4], + SPINOR_OP_PP_1_4_4, SNOR_PROTO_1_4_4); + + return 0; +} + static const struct spi_nor_fixups mx25l25635_fixups = { .post_bfpt = mx25l25635_post_bfpt_fixups, .post_sfdp = macronix_qpp4b_post_sfdp_fixups, @@ -96,6 +115,10 @@ static const struct spi_nor_fixups mx25l3255e_fixups = { .late_init = mx25l3255e_late_init_fixups, }; +static const struct spi_nor_fixups mx25l12805d_4pp3b_fixups = { + .post_sfdp = mx25l12805d_4pp3b_post_sfdp_fixups, +}; + static const struct flash_info macronix_nor_parts[] = { { .id = SNOR_ID(0xc2, 0x20, 0x10), @@ -130,9 +153,10 @@ static const struct flash_info macronix_nor_parts[] = { .size = SZ_8M, .no_sfdp_flags = SECT_4K, }, { - /* MX25L12805D */ + /* MX25L12805D, MX25L12833F, MX25L12845G */ .id = SNOR_ID(0xc2, 0x20, 0x18), .flags = SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP, + .fixups = &mx25l12805d_4pp3b_fixups, }, { /* MX25L25635E, MX25L25645G */ .id = SNOR_ID(0xc2, 0x20, 0x19), -- 2.25.1 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/ From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 026AB4A33F3 for ; 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[211.75.127.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c164fa0236sm86673185ad.33.2026.06.05.01.50.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Jun 2026 01:50:51 -0700 (PDT) Received: from hqs-appsw-a2o.mp600.macronix.com (unknown [172.17.236.67]) by twhmp6px (Postfix) with ESMTPS id AD5854163B72; Fri, 5 Jun 2026 16:50:49 +0800 (CST) From: Cheng Ming Lin To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, alvinzhou@mxic.com.tw, Cheng Ming Lin Subject: [PATCH v3 1/2] mtd: spi-nor: Add support for MX25L12833F and MX25L12845G Date: Fri, 5 Jun 2026 16:48:36 +0800 Message-Id: <20260605084837.1875896-2-linchengming884@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260605084837.1875896-1-linchengming884@gmail.com> References: <20260605084837.1875896-1-linchengming884@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Cheng Ming Lin Add support for Macronix MX25L12833F and MX25L12845G SPI NOR flashes. These parts share the same JEDEC ID (0xc2, 0x20, 0x18) as the legacy MX25L12805D. The newer flashes support SFDP and 1-4-4 Page Program in 3-byte address mode, but this 4PP capability is not defined in their SFDP tables. Conversely, the legacy MX25L12805D lacks SFDP support entirely and does not support 4PP. To safely enable 4PP for the newer flashes without breaking the legacy part, introduce a post_sfdp fixup. Since the legacy MX25L12805D does not support SFDP, it falls back to static parameters and will never execute the post_sfdp hook. The newer flashes will successfully parse the SFDP, trigger the hook, and safely append the SNOR_HWCAPS_PP_1_4_4 capability. Signed-off-by: Cheng Ming Lin --- drivers/mtd/spi-nor/macronix.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c index e97f5cbd9..1adb79832 100644 --- a/drivers/mtd/spi-nor/macronix.c +++ b/drivers/mtd/spi-nor/macronix.c @@ -83,6 +83,25 @@ mx25l3255e_late_init_fixups(struct spi_nor *nor) return 0; } +static int +mx25l12805d_4pp3b_post_sfdp_fixups(struct spi_nor *nor) +{ + struct spi_nor_flash_parameter *params = nor->params; + + /* + * JEDEC ID 0xc22018 is shared by MX25L12805D (no SFDP, no 4PP) and + * MX25L12833F/MX25L12845G (support SFDP and 4PP in 3-byte mode). + * The legacy 05D lacks SFDP and will not execute this hook. For + * the newer flashes, 3-byte 1-4-4 PP is not defined in SFDP, so + * we safely enable it here. + */ + params->hwcaps.mask |= SNOR_HWCAPS_PP_1_4_4; + spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_4_4], + SPINOR_OP_PP_1_4_4, SNOR_PROTO_1_4_4); + + return 0; +} + static const struct spi_nor_fixups mx25l25635_fixups = { .post_bfpt = mx25l25635_post_bfpt_fixups, .post_sfdp = macronix_qpp4b_post_sfdp_fixups, @@ -96,6 +115,10 @@ static const struct spi_nor_fixups mx25l3255e_fixups = { .late_init = mx25l3255e_late_init_fixups, }; +static const struct spi_nor_fixups mx25l12805d_4pp3b_fixups = { + .post_sfdp = mx25l12805d_4pp3b_post_sfdp_fixups, +}; + static const struct flash_info macronix_nor_parts[] = { { .id = SNOR_ID(0xc2, 0x20, 0x10), @@ -130,9 +153,10 @@ static const struct flash_info macronix_nor_parts[] = { .size = SZ_8M, .no_sfdp_flags = SECT_4K, }, { - /* MX25L12805D */ + /* MX25L12805D, MX25L12833F, MX25L12845G */ .id = SNOR_ID(0xc2, 0x20, 0x18), .flags = SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP, + .fixups = &mx25l12805d_4pp3b_fixups, }, { /* MX25L25635E, MX25L25645G */ .id = SNOR_ID(0xc2, 0x20, 0x19), -- 2.25.1